Silver alloy material, circuit substrate, electronic device, and method for manufacturing circuit substrate

ABSTRACT

A circuit substrate of the present invention uses as component materials for gate lines and gate electrodes, silver alloy material containing silver as a main component, and at least one element selected from the group consisting of tin, zinc, lead, bismuth, indium, and gallium. It is especially preferable that the silver alloy material mainly consisting of silver and containing indium is used for the gate lines and the gate electrodes. With this, it is possible to provide silver alloy material whose resistance value, adhesion, plasma resistance, and reflection characteristics can be appropriately adjusted by the adjustment of the content of indium. Further, it is also possible to apply the alloy in accordance with the characteristic required for each part of the circuit substrate.

This Nonprovisional application claims priority under 35 U.S.C. § 119(a) on Patent Application No. 200806/2003 filed in Japan on Jul. 23, 2003, Patent Application No. 200815/2003 filed in Japan on Jul. 23, 2003, Patent Application No. 185228/2004 filed in Japan on Jun. 23, 2004, and Patent Application No. 185264/2004 filed in Japan on Jun. 23, 2004, the entire contents of which are hereby incorporated by reference.

FIELD OF THE INVENTION

The present invention relates to a silver alloy material. The present invention relates in particular to a silver alloy material which composes lines and/or electrodes on a circuit substrate that uses an insulation substrate; a circuit substrate whose lines and/or electrodes are formed using either the above-mentioned material or fluid material such as silver alloy fluid; a method for manufacturing the circuit substrate; and an electronic device using the circuit substrate, such as a display device, a liquid crystal display device, and an image input device.

BACKGROUND OF THE INVENTION

A liquid crystal display as an electronic device is provided as a circuit substrate, a TFT array substrate that includes many TFTs (thin film transistors), lines, and the like.

Conventionally, the TFT array substrate is manufactured by sequential steps as described in Non-Patent Publication 1 (Flat Panel Display 1999, page 129; Nikkei Micro Device (ed.), Nikkei Business Publications, Inc.). In this method, photolithography is required to be performed about five times.

The conventional method for manufacturing the TFT array substrate using photolithography requires many vacuum equipment including film forming equipment used for film forming steps, etching equipment such as dry etching equipment, and the like. Accordingly, a huge cost of equipment is required in the manufacturing of TFT array substrates in response to recent demands for TFT array substrates having larger size.

In order to solve the foregoing problems, a technique for forming the lines and the like using an ink-jet method is suggested. In this technique, an affinity area and a non-affinity area with respect to a material for forming lines are formed on a substrate on which the lines are to be formed, and the lines are formed in such a manner that droplets of the wiring material are dropped to the affinity area using the ink-jet method, as disclosed in Patent Publication 1 (Japanese Unexamined Patent Publication No. 11-204529 (Tokukaihei 11-204529), published on Jul. 30, 1999).

Further, Patent Publication 2 (Japanese Unexamined Patent Publication No. 2000-353594, (Tokukai 2000-353594), published on Dec. 19, 2000) also discloses a wiring forming technique using the ink-jet method. In this technique, banks are formed on both sides of a line formation area, Here, upper portions of the banks are lyophobic and lower portions of the banks are lyophilic in order to prevent the wiring material from spilling over the line formation area.

As a material for forming lines using the ink-jet method as described above, used is a fluid metal-containing material (ink) in which nanoparticles of silver or gold are dispersed in a solvent, as described in Non-Patent Publication 2 (Nikkei Electronics (Jun. 17, 2002), Nikkei Business Publications, Inc.). This material is dropped to a predetermined position on a substrate, and subject to processing such as baking. With this, the metal contained in the material emerges and forms the lines and the like. As metal that can be processed into the fluid metal-containing material as described above, palladium, platinum, and the like, are mentioned other than silver and gold. In view of the price of the raw materials, however, only silver is realistic.

Accordingly, as a material for forming the lines on the TFT array substrates or other circuit substrates, use of silver, which is applicable to the ink-jet method, has been considered.

Conventionally, aluminum has been widely used as the material for the lines and a light reflecting film on a circuit substrate such as the TFT array substrate. Silver is known to have more excellent properties than aluminum in that silver has low electric resistance, and high reflectance with respect to the visible light range.

As described above, silver is a notable material for the lines on circuit substrates. However, the usable range of silver is limited because of the properties of silver. Silver significantly lacks heat resistance. If silver is formed into a film on a glass substrate using an evaporation method, a sputtering method, or other methods, for example, the silver film generates grain growth and clouded surface when baked at about 250° C. Further, silver has weak adhesion to the glass substrate.

In the manufacturing of TFT array substrates, in particular, dry etching is used many times for the etching of an insulation film, etc. Silver has remarkably low resistance to this environment (plasma resistance). Therefore silver cannot be directly used as a material for forming the lines on TFT array substrates.

Further, conventional silver has low heat resistance, and the reflectance of the silver is remarkably lowered after the silver is baked at 200° C., for example. Hence, conventional silver cannot be used if heat resistance is required during the manufacturing process. For example, it has been difficult to use silver as a material for a light reflecting film provided on a TFT array substrate in a reflection type liquid crystal display device, for example.

In relation to the line formation using silver, Patent Publication 3 (Japanese Unexamined Patent Publication No. 2003-80694 (Tokukai 2003-80694), published on Mar. 19, 2003) discloses a method for forming lines without using the banks.

Accordingly, as a material for forming the lines on the TFT array substrates, use of silver, which is applicable to the ink-jet method, has been considered.

Incidentally, when a thin film layered substrate, such as a TFT array substrate used for liquid crystal display device is formed, the performance required for the lines includes low resistance; smooth flatness; resistance to process gas for etching, etc., and to plasma that uses the process gas; adhesion to an underlying layer; low electric contact property with a different type of material, namely, low contact resistance; resistance that does not cause unwanted diffusion; and corrosion resistance.

However, it is difficult for one type of material to cover all of the performances as described above. Therefore, in sputtering, evaporation, and CVD film formation, a simple substance or an alloy material having performances in accordance with usage is formed into films in layers, and then patterned through a photolighography step and an etching step.

Further, a method for forming lines using the ink-jet method can simplify the method. In this method, silver material as a material used for the ink-jetting is used as particle colloid material in which particles of the silver material are dispersed in dispersion medium. This is a notable material for the lines on the circuit substrate, but has a limited range of usage because of the properties of the material.

Silver significantly lacks heat resistance depending on temperature. For example, if silver is formed into a film on a glass substrate using an evaporation method, a sputtering method, or other methods, for example, the silver film remarkably generates grain growth when baked at about 250° C. With this, the smooth surface of the silver film becomes rough and becomes clouded.

Further, when used as a thin film, silver is required to have adhesion to glass. However, silver as an application material, in particular, cannot have an effect of implanting into the substrate when formed into the film. Consequently, the silver has weak adhesion to the glass substrate, thus having problems in processability and stability. Further, if the baking is used to improve the adhesion, the surface flatness of the silver film deteriorates due to the grain growth properties of silver as described above.

Further, there is also a problem in using silver to form lines on a TFT array substrate. For example, dry etching is performed many times for the etching of an insulation film, etc., in the manufacturing of the TFT array substrate. When exposed to plasma in the dry etching gas, the silver film is deteriorated and separated because of oxidation, etc. Therefore there is a problem in immediately using silver as the wiring material.

Therefore, in order to solve the foregoing problems in cases where silver is used as the wiring material, it is necessary to perform the processing for improving the adhesion on the insulation substrate; further, it is necessary to form a thin film as a passivation film on the silver lines so as to prevent the deterioration of surface flatness of the silver film due to heat, and the deterioration and separation of the silver film due to the etching gas. In other words, there is a problem that thin films are layered on the insulation substrate. This increases the number of steps for manufacturing the circuit substrate, thereby increasing the cost.

SUMMARY OF THE INVENTION

The present invention has an objective to provide a silver alloy material that can realize a material having heat resistance and strong adhesion to a glass substrate as well as high plasma resistance and good light reflectance. The present invention also has an objective to provide a circuit substrate that can obviate a multi-layer structure of thin films so as to prevent the increase in the number of steps and cost for manufacturing the circuit substrate; a method for manufacturing the circuit substrate; and an electronic device.

As a result of assiduous study in order to achieve the foregoing objectives, the inventors of the present invention found that in a case where particles of alloy containing silver as its main component and indium are used as a material for forming lines or electrodes on an insulation substrate, the adhesion of the lines and electrodes to the insulation substrate, as well as the heat resistance and plasma resistance of the lines and electrodes improved, compared with a case where particles consisting only silver is used as a material for forming the lines or electrodes on the insulation substrate. Further, the inventors found that the similar effects can be achieved by using alloy in which tin, zinc, lead, bismuth, or gallium, instead of indium, is added to silver.

Further, the inventors of the present invention found that it is possible to obtain a silver alloy film retaining high visible light reflectance after baked at 200° C. or at 300° C. by adding an appropriate amount of indium to silver. Further, the inventors found that, because the silver alloy film as described above has high reflectance as a whole compared with aluminum conventionally used for a light reflecting film, brighter display can be achieved when the silver alloy film is used as light reflective electrodes, etc., in a reflection type liquid crystal display device, for example.

As described above, a silver alloy material of the present invention for composing lines and/or electrodes formed on an insulation substrate is arranged so as to contain silver as a main component; and at least one element selected from the group consisting of tin, zinc, lead, bismuth, indium, and gallium.

With the material as arranged above, it is possible to form lines and/or electrodes that has low electric resistance, as well as high process resistance such as heat resistance, adhesion to a glass substrate, and plasma resistance.

Further, as a result of assiduous study, the inventors of the present invention found that it is possible to reduce the number of steps and cost for manufacturing a circuit substrate by adjusting the characteristics of a same line in accordance with the characteristic required for each part of the line.

A circuit substrate of the present invention including lines formed on a substrate is arranged so that at least two portions in a same line have different characteristics from one another.

Here, the same line means a line having continuous shape, and a unit of a plurality of lines that form the circuit substrate.

It is possible to change characteristics of one portion from another in the same line by causing the portions to have different composition ratios from one another, or by causing the portions to have different component materials from one another.

For a fuller understanding of the nature and advantages of the invention, reference should be made to the ensuing detailed description taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view of a circuit substrate in accordance with an embodiment of the present invention.

FIG. 2 is a cross-sectional view of the circuit substrate corresponding to line A-A of FIG. 1.

FIG. 3(a) is a plan view showing the circuit substrate of FIG. 1 in the vicinity of a terminal section.

FIG. 3(b) is a cross-sectional view of the circuit substrate corresponding to line B-B of FIG. 3(a).

FIG. 4 is a plan view of a TFT array substrate showing an example of the circuit substrate shown in FIG. 1.

FIG. 5 is a block diagram schematically showing a manufacturing apparatus for manufacturing a circuit substrate of the present invention.

FIG. 6 is a process chart showing a manufacturing process of a circuit substrate of the present invention.

FIG. 7(a) is a plan view showing a pixel section after a gate line pre-processing step.

FIG. 7(b) is a plan view showing the pixel section after the gate line formation step.

FIG. 7(c) is a cross-sectional view of the circuit substrate corresponding to line C-C of FIG. 7(b).

FIG. 8(a) is a plan view showing the terminal section after the gate line pre-processing step.

FIG. 8(b) is a plan view showing the terminal section after the gate line formation step.

FIG. 8(c) is a cross-sectional view of the circuit substrate corresponding to line D-D of FIG. 8(b).

FIGS. 9(a) through 9(d) are diagrams showing a process of forming a lyophilic and lyophobic area in the gate line pre-processing step.

FIG. 10(a) is a plan view showing the pixel section after a gate insulation film and semiconductor film formation step.

FIG. 10(b) is a cross-sectional view corresponding to line E-E of FIG. 10(a).

FIG. 11(a) is a plan view showing the terminal section after the gate insulation film and semiconductor film formation step.

FIG. 11(b) is a cross-sectional view corresponding to line F-F of FIG. 11(a).

FIG. 12(a) is a plan view showing the pixel section after a gate insulation film and semiconductor film processing step.

FIG. 12(b) is a cross-sectional view corresponding to line G-G of FIG. 12(a).

FIG. 13(a) is a plan view showing the terminal section after the gate insulation film and semiconductor film processing step.

FIG. 13(b) is a cross-sectional view corresponding to line H-H of FIG. 13(a).

FIG. 14(a) is a plan view showing the pixel section after a source and drain lines pre-processing step.

FIG. 14(b) is a plan view showing the pixel section after a source and drain lines formation step.

FIG. 14(c) is a cross-sectional view corresponding to line I-I of FIG. 14(b).

FIG. 15 shows the pixel section after a channel section processing step, and a cross-sectional view corresponding to line I-I of FIG. 14(b).

FIG. 16(a) is a plan view showing the pixel section after a passivation film and interlayer insulation layer formation step.

FIG. 16(b) is a cross-sectional view corresponding to line J-J of FIG. 16(a).

FIG. 17(a) is a plan view showing the terminal section after the passivation film and interlayer insulation layer formation step.

FIG. 17(b) is a cross-sectional view corresponding to line K-K of FIG. 17(a).

FIG. 18(a) shows the pixel section after a passivation film processing step, and a cross-sectional view corresponding to line J-J of FIG. 16(a).

FIG. 18(b) shows the terminal section after the passivation film processing step, and a cross-sectional view corresponding to line K-K of FIG. 17(a).

FIG. 19(a) is a plan view showing a terminal section of a circuit substrate in accordance with another embodiment of the present invention.

FIG. 19(b) is a cross-sectional view corresponding to line L-L of FIG. 19(a).

FIG. 20 is a graph showing a visible light reflectance of a silver film of Comparative Example 1 shown in Table 1.

FIG. 21 is a graph showing a visible light reflectance of an aluminum film of Comparative Example 3 shown in Table 1.

FIG. 22 is a graph showing a visible light reflectance of a silver alloy film of Example 7 (containing 0.05% of indium by weight) shown in Table 1.

FIG. 23 is a graph showing a visible light reflectance of a silver alloy film of Example 8 (containing 0.2% of indium by weight) shown in Table 1.

FIG. 24 is a graph showing a visible light reflectance of a silver alloy film of Example 3 (containing 0. 5% of indium by weight) shown in Table 1.

FIG. 25 is a graph showing a visible light reflectance of a silver alloy film of Example 4 (containing 1.6% of indium by weight) shown in Table 1.

FIG. 26(a) is a plan view showing the pixel section after a gate line formation step.

FIG. 26(b) is a cross-sectional view corresponding to line M-M of FIG. 26(a).

FIG. 27(a) is a plan view showing the terminal section after the gate line formation step.

FIG. 27(b) is a cross-sectional view corresponding to line N-N of FIG. 27(a).

FIG. 28 is a plan view showing a circuit substrate in accordance with a further embodiment of the present invention.

FIG. 29 is a cross-sectional view of the circuit substrate corresponding to line 0-0 of FIG. 28.

FIG. 30(a) is a plan view showing the circuit substrate of FIG. 28 in the vicinity of a terminal section.

FIG. 30(b) is a cross-sectional view corresponding to line P-P of FIG. 30(a).

FIG. 31(a) is a plan view showing another example of the circuit substrate of FIG. 1 in the vicinity of a terminal section.

FIG. 31(b) is a cross-sectional view corresponding to line Q-Q of FIG. 31(a).

FIGS. 32(a) through 32(e) are diagrams showing a process for forming a line section and a terminal section of the circuit substrate of the present invention.

FIG. 33(a) is a diagram where a material M is used to form the line section.

FIG. 33(b) is a diagram where a material N is used to form the terminal section.

FIGS. 34(a) through 34(c) are diagrams showing states of a boundary section where the materials M and N contact with each other.

FIG. 35 is a diagram schematically showing gate lines in the circuit substrate of the present invention.

FIG. 36(a) is a diagram showing a pattern of a conventional line.

FIG. 36(b) is a diagram showing a pattern of a line of the present invention.

FIGS. 37(a) and 37(b) are diagrams showing another example of line formation on the circuit substrate of the present invention.

FIGS. 38(a) and 38(b) are diagrams showing a further example of line formation on the circuit substrate of the present invention.

FIGS. 39(a) and 39(b) are diagrams showing yet another example of line formation on the circuit substrate of the present invention.

FIGS. 40(a) through 40(c) are diagrams showing still another example of line formation on the circuit substrate of the present invention.

FIG. 41(a) is a plan view showing the pixel section after a gate line formation step.

FIG. 41(b) is a cross-sectional view corresponding to line R-R of FIG. 41(a).

FIG. 42(a) is a plan view showing the terminal section after the gate line formation step.

FIG. 42(b) is a cross-sectional view corresponding to line S-S of FIG. 42(a).

DESCRIPTION OF THE EMBODIMENTS

[First Embodiment]

The following will explain an embodiment of the present invention.

In the present embodiment, a silver alloy material of the present invention will be explained first, and then a TFT array substrate and liquid crystal display device using the silver alloy material will be explained.

A silver alloy material of the present invention which composes lines and/or electrodes formed on an insulation substrate such as a glass substrate is arranged so as to contain silver as a main component and at least one element selected from the group consisting of tin, zinc, lead, bismuth, indium, and gallium.

With the silver alloy material as arranged above, it is possible to form lines and/or electrodes having low electric resistance, as well as high process resistance such as heat resistance, adhesion to the glass substrate, and plasma resistance.

With reference to Examples 1 through 9 and Comparative Examples 1 and 2, the following will demonstrate the above-described advantages of the silver alloy material of the present invention.

The process resistance of the silver alloy material of the present invention was evaluated in the following state. Namely, the silver alloy material was produced in a manner as described below and formed into a film on an insulation substrate.

The silver alloy material of the present invention was produced and formed into the film on the insulation substrate by an evaporation method using an electron beam evaporation equipment (High-Vacuum evaporation system EBX-10D, manufactured by ULVAC, Inc.).

First, as an evaporation source, raw materials in lump or granular form, such as silver whose purity is not less than 99.9%, tin, zinc, lead, bismuth, indium, and gallium, were mixed in a predetermined mixing ratio by weight.

Next, the mixed materials were placed in a crucible made of molybdenum, and then fused in a vacuo of less than 1×10⁻⁵ Torr and alloyed.

Lastly, after the complete fusion of the mixed material was confirmed, the material was formed into a film on a nonalkali glass substrate. Note that, a temperature of the glass substrate when the material was formed into the film was set to 100° C. Further, a thickness of the alloy film formed on the glass film was entirely set to about 0.2 μm.

In the present embodiment, the foregoing method was employed for producing the alloy and forming the alloy into the film, but the method is not limited to this. The method may be a sputtering method using solid solution, sintered product, or the like, as a target; an application method of a fluid liquid material that contains an appropriate concentration of a metal element; or other methods.

The composition of the thus produced silver alloy film was checked using Auger electron spectroscopy equipment (SAM670, manufactured by Perking Elmer Corporation). The composition was even without non-uniformity in a direction of the film thickness, but the overall composition ratio of the produced silver alloy film was slightly different from the mixing ratio of the raw materials. However, the difference was so insignificant as to cause no influence on the objective, means, effects, etc., of the present invention. The produced silver alloy film is only a typical example of the present invention.

Quantitative analysis by ICP spectrometry was further performed with respect to each alloy film composed of silver and indium, in order to determine the composition of the alloy film more accurately. The quantitative analysis was performed by the following method.

First, a portion of the silver alloy film formed on the nonalkali glass substrate was exfoliated as a sample by a metal spoon. The silver alloy film on the glass substrate before exfoliated had a thickness of about 0.2 μm. An amount of the sample obtained was about 10 mg in each Example. Subsequently, the sample was dissolved in 50 ml of 3N nitric acid so that a measurement liquid for the ICP spectrometry was prepared. SPS-1700HVR manufactured by SII Nanotechnology Inc. was used as measurement equipment, and argon was used as plasma gas.

In the present embodiment, adhesion, heat resistance, electric resistivity, and plasma resistance were evaluated as the process resistance of the silver alloy film. These items are most fundamental properties required for the lines and the like on circuit substrates. These items will be explained in detail as below.

The adhesion was checked in such a manner that the silver alloy was formed into a film directly on a nonalkali glass substrate.

When the silver alloy film is to be used on a circuit substrate as in the present invention, the adhesion to the glass substrate is a useful index.

Here, the adhesion was tested with respect to the alloy film on the substrate after baked for one hour at 200° C. in a nitrogen atmosphere. After the baking, cuts were provided to a surface of the film. Then, adhesive tape was adhered to the surface of the film, and separated in such a manner as to peel off the surface of the film. If any portion of the surface of the film was peeled off, the adhesion was judged as poor. Only if the surface of the film was not peeled off at all, the adhesion was judged as good.

The heat resistance was evaluated in such a manner that a surface of the film after baked for one hour at 300° C. in a nitrogen atmosphere was observed through an electron microscope (S-4100, manufactured by Hitachi, Ltd.). The heat resistance was judged as good if no unevenness occurred on the surface of the film, and judged as fair if protrusions having heights of not more than the film thickness occurred on a part of the surface of the film. The heat resistance was judged as poor with respect to the other results.

The electric resistivity was evaluated with respect to the substrate after baked for one hour at 200° C. in a nitrogen atmosphere. A sheet resistance value obtained by a four-point probe method using a measurement machine (Loresta-GP, manufactured by Mitsubishi Chemical Corporation), and the thickness of the film separately measured were used to obtain the electric resistivity.

The plasma resistance was evaluated using dry etching equipment (RIE (reactive ion etching method)). Specifically, after the substrate was placed in a process chamber, discharging was performed while introducing various kinds of etching gas into the process chamber.

The conditions for the evaluation were three conditions in which chlorine gas (Cl₂) gas; mixed gas of carbon tetrafluoride (CF₄) gas and oxygen (O₂) gas; and oxygen (O₂) gas were respectively introduced.

Hereinafter, these three conditions are referred to as Cl₂ condition, CF₄+O₂ condition, and O₂ condition, respectively. The discharging periods were 180 seconds, 60 seconds, and 60 seconds, respectively. Note that, these discharging periods were intentionally set to harsh conditions in view of a five-mask process to be described later.

For judgment as to the plasma resistance, the sheet resistance value of the film was checked. The sheet resistance value was measured as in the measurement of the electric resistivity. The plasma resistance was judged as good if the sheet resistance value was not more than 2.5 times as the sheet resistance value before the processing. The plasma resistance was judged as fair if the sheet resistance value was more than 2.5 times and not more than 7 times as the sheet resistance value before the processing. The plasma resistance was judged as poor with respect to the other results.

These evaluation items are only examples that are set to demonstrate the properties of the silver alloy material of the present invention. For the purpose of clear distinction, each of the conditions is intentionally set to be harsher than an assumed use condition. The evaluation of these items is not necessarily required in carrying out the present invention, and the details such as the observing means, judgment standards, and conditions are only examples. The applicable range of the present invention is not limited by these evaluation items and each of the conditions.

Examples of evaluation results of the silver alloy materials of the present invention will be shown in Tables 1 and 2.

In Tables, Comparative Example 1 is an example regarding a metal film made of only silver, and Comparative Example 2 is an example regarding a silver alloy film prepared by mixing 2% of aluminum by weight into the evaporation source. Examples 1 through 9 are examples regarding silver alloy films prepared by mixing into the evaporation source, 10% of tin by weight, 10% of zinc by weight, 1% of indium by weight, 3% of indium by weight, 5% of indium by weight, 10% of indium by weight, 0.1% of indium by weight, 0.3% of indium by weight, and 20% of indium by weight, respectively, with respect to silver. Examples 1 through 9 are examples of the present invention. Note that, each of the raw materials should contain impurities though in very small quantities, but the quantities are so infinitesimal as to have no influence on the results. Thus, the description of the impurities is omitted here.

First, Table 1 shows evaluation results with respect to the ICP spectrometry values, adhesion, and heat resistance. TABLE 1 ICP MIXING RATIO OF SPECTROMETRY EVAPORATION SOURCE ADHESION HEAT VALUES NON-SILVER (AFTER RESISTANCE NON-SILVER ELEMENT BAKED (AFTER ELEMENT MIXING FOR 1 BAKED FOR RATIO TO AMOUNT HOUR AT 1.5 HOUR AT SILVER TYPE [WEIGHT %] SILVER 200° C.) 300° C.) [WEIGHT %] COMPARATIVE (NONE) 0 REST POOR POOR — EXAMPLE 1 EXAMPLE 1 TIN 10 REST GOOD FAIR — EXAMPLE 2 ZINC 10 REST GOOD FAIR — EXAMPLE 3 INDIUM 1 REST GOOD FAIR 0.5 EXAMPLE 4 INDIUM 3 REST GOOD GOOD 1.6 EXAMPLE 5 INDIUM 5 REST GOOD GOOD 3.4 EXAMPLE 6 INDIUM 10 REST GOOD GOOD 9.3 COMPARATIVE ALUMINUM 2 REST GOOD FAIR — EXAMPLE 2 EXAMPLE 7 INDIUM 0.1 REST POOR FAIR 0.05 EXAMPLE 8 INDIUM 0.3 REST POOR FAIR 0.2 EXAMPLE 9 INDIUM 20 REST GOOD GOOD —

The results of the quantitative analysis by the ICP spectrometry as explained above were such that contents of indium with respect to silver were 0.5% by weight, 1.6% by weight, 3.4% by weight, 9.3% by weight, 0.05% by weight, and 0.2% by weight in Examples 3 through 8, respectively.

As shown in Table 1, the film made of only silver in Comparative Example 1 was poor in both the adhesion and heat resistance. Silver remarkably lacks heat resistance such that a surface of the silver film clearly becomes clouded under more modest conditions, namely, when baked for one hour at 250° C. This is one of the reasons why it is difficult to use silver as the lines.

On the other hand, the adhesion to the glass substrate improved as a whole with respect to the silver alloy films in which tin, zinc, and indium were added to silver, as shown in Examples 1 through 9 of the present invention. In terms of the addition of indium, the adhesion clearly improved with respect to the silver alloy films containing indium in an amount of about not less than 0.5% by weight with respect to silver, as shown in Example 3, etc.

The heat resistance also improved as a whole in Examples 1 through 9 of the present invention. In Examples 7 and 8, especially, the heat resistance improved even though the contents of indium with respect to silver had very small spectrometry values, namely, 0.05% by weight and 0.2% by weight, respectively. This reveals that the addition of indium is quite effective in improving the heat resistance.

The adhesion improved presumably because the element such as tin, zinc, and indium that makes up the silver alloy of the present invention diffused into the glass substrate, though in very small quantities, and eliminated the interface. With this, the adhesion energy became large close to the cohesive energy of the bulk. This idea is supported by the fact that the adhesion of the silver alloy film of the present invention was larger after baked for one hour at 200° C. than after formed into the film at the substrate temperature of 100° C. Namely, the present invention is based on the principle to achieve adhesion by the diffusion of tin, zinc, indium, etc., in the silver alloy film.

Note that, the scope of the present invention is not limited to the method for achieving the adhesion by forming and then baking the film as in the present examples, and includes a method for achieving the adhesion by sufficiently raising the substrate temperature during the film formation.

On the other hand, the heat resistance improved presumably because tin, zinc, or indium was contained in the film, so that the lattice constant and grain size of the crystal changed. With this, the movement of silver molecules in the film was restricted and the grain growth was not easily occur.

It is also important in the silver alloy material of the present examples that the composition of the obtained film was set in a range where the mixed element was melted into the silver crystal so as to produce a primary solid solution (solid solution). If the composition is set within the range where the primary solid solution is produced, an intermediate solid solution or intermetallic compound whose crystal structure differs from the silver crystal is not easily extracted even after the film is baked, and new grain growth of the crystal is suppressed on a surface of the film. Therefore the surface property of the film does not change after the baking, resulting in the high heat resistance.

The range of the composition that produces the primary solid solution depends on the surrounding temperature, but in terms of tin, zinc, and indium, the contents are in ranges of less than 11% to 14% by weight, less than 25% to 39% by weight, and less than 27% to 28% by weight, respectively, with respect to silver.

As described above, the evaluation results shown in Table 1 revealed that the silver alloy material of the present invention has an improved heat resistance compared with silver, and the silver alloy material alloyed with indium, in particular, has an improved adhesion if the content of indium is not less than 0.5% by weight.

Further, the silver alloy material of the present invention may be an alloy of gallium that is a congener of indium in the periodic table of the elements, lead that is a congener of tin in the periodic table of the elements, or bismuth whose property is similar to lead. This silver alloy material also exhibits excellent adhesion and heat resistance.

Next, Table 2 shows evaluation results of the electric resistivity and plasma resistance. TABLE 2 ELECTRIC PLASMA RESISTANCE RESISTIVITY Cl₂ CF₄ + O₂ O₂ [μΩcm] CONDITION CONDITION CONDITION COMPARATIVE 1.9 POOR POOR POOR EXAMPLE 1 EXAMPLE 1 2.8 POOR POOR FAIR EXAMPLE 2 6.8 GOOD POOR FAIR EXAMPLE 3 2.7 GOOD POOR POOR EXAMPLE 4 4.0 GOOD POOR GOOD EXAMPLE 5 6.1 GOOD GOOD GOOD EXAMPLE 6 12.3 GOOD GOOD GOOD COMPARATIVE 2.4 POOR POOR POOR EXAMPLE 2 EXAMPLE 7 2.2 POOR POOR POOR EXAMPLE 8 2.3 POOR POOR POOR EXAMPLE 9 21.8 GOOD GOOD GOOD

The evaluation results shown in Table 2 reveals that except in Examples 6 and 9, the electric resistivity was generally a low electric resistivity of not more than 7 μΩcm which is equal to or less than that of conventional aluminum alloy. This shows that the silver alloy material of the present invention is suitable for the lines and the like having low electric resistance. Note that, the silver alloy material having the electric resistivity of about not more than 10 μΩcm is practicable as a material for a circuit substrate for a large-sized display device.

In Examples 7, 8, and 3, in particular, the contents of indium were in a ratio of not more than 0.5% by weight with respect to silver, and the electric resistivities were very low, namely, 2.2 μΩcm, 2.3 μΩcm, and 2.7 μΩcm, respectively. Aluminum has an electric resistivity of 2.7 μΩcm in bulk state, and cannot have an electric resistivity of not more than 2.7 μΩcm when formed into a thin film. Therefore the foregoing low electric resistance cannot be achieved by the use of aluminum alone.

Therefore, among the silver alloy materials of the present invention, the silver alloy material containing indium in a ratio of not more than 0.5% by weight with respect to silver, especially, can form the lines having low electric resistance that cannot be achieved by conventional aluminum lines. The silver alloy material of the present invention is appropriately used to manufacture a circuit substrate whose lines are especially required to have low electric resistance, as in a liquid crystal display device used for a liquid crystal TV, for example.

However, because of the low indium content, this silver alloy material does not have sufficient plasma resistance, and generally requires another metal film to be layered thereon. Further, because of the low indium content, the silver alloy material does not have sufficient adhesion to the substrate, and may require pre-processing and the like.

The plasma resistance improved in Examples 1 through 6 and 9 of the present invention. In terms of indium, in particular, the plasma resistance improved if the content of indium was not less than about 0.5% by weight. However, in the strict sense, some of the alloy materials may have a poor plasma resistance depending on plasma conditions.

In Comparative Example 1 where silver was used alone and in Comparative Example 2 where the silver was alloyed with aluminum, the plasma resistance was all judged as poor. In contrast, the plasma resistance was judged as fair in the O₂ condition in Example 1, and judged as good in the Cl₂ condition and fair in the O₂ condition in Example 2. Especially useful silver alloys are the silver alloys in Examples 3 through 6 and 9, which are arranged to contain indium. These silver alloys had a significant effect on the improvement of the plasma resistance such that all of these silver alloys in these Examples had good plasma resistance in the Cl₂ condition. Silver alloy in Example 5 having a comparatively high indium content had good plasma resistance with respect to all of the plasma resistance conditions, and also had a low electric resistivity of 6.1 μΩcm. Therefore the silver alloy in Example 5 proved to be very useful by having both process resistance and low electric resistance. On the other hand, in Examples 6 and 9, though the electric resistivities are comparatively high in Table 2, the plasma resistance further improved than in Example 5.

The plasma resistance improved as described above presumably because a compound of (A) tin, zinc, indium, etc., in the silver alloy and (B) chlorine, fluorine, oxygen, etc., supplied from the gas introduced into the chamber had a lower vapor pressure than that of silver, and serves as a passivation layer for hindering erosion of the surface of the film.

On the other hand, the plasma resistance of the silver alloy material containing indium in a ratio of not more than 0.5% by weight with respect to silver, as in Examples 7 and 8, was all poor.

As described above, if the silver alloy material of the present invention contains indium in a ratio of not less than 0.5% by weight, in particular, the silver alloy material has both plasma resistance and low electric resistance. Therefore the silver alloy material of the present invention is a useful material for, in particular, the lines on a TFT array substrate which in most cases require plasma resistance. However, the constituent elements such as tin, zinc, and indium and their ratios in the silver alloy material need not satisfy all the characteristics in the tables, and may be selected so as to satisfy required characteristics according to circumstances.

Further, if the silver alloy material of the present invention contains indium in a ratio of not more than 0.5% by weight, in particular, the silver alloy material has an electric resistivity of not more than 2.7 μΩcm, namely, has very low electric resistance. Therefore the silver alloy material of the present invention is appropriately used for a circuit substrate of a liquid crystal display device used for a liquid crystal TV, in particular.

Further, the silver alloy material of the present invention may be an alloy of gallium that is a congener of indium in the periodic table of the elements, lead that is a congener of tin in the periodic table of the elements, or bismuth whose property is similar to lead. This silver alloy material also exhibits excellent adhesion and heat resistance.

The foregoing revealed that the silver alloy material of the present invention is a very useful material having process resistance such as adhesion, heat resistance, low electric resistance, and plasma resistance.

Note that, these evaluation results were obtained under conditions that were set to demonstrate the properties of the silver alloy material of the present invention. For the purpose of clear distinction between the materials, each of the conditions was intentionally set to be harsher than an assumed use condition. The applicable range of the present invention is not limited to the results shown in Tables 1 and 2.

The silver alloy material of the present invention may be arranged so as to further include an element selected from the group consisting of aluminum, copper, nickel, gold, platinum, palladium, cobalt, rhodium, iridium, ruthenium, osmium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, and neodymium. The addition of these elements further improves the heat resistance, plasma resistance, and adhesion of the silver alloy material, so that an optimum alloy material is obtained.

When used as a component material of the lines and the like on a TFT array substrate, the silver alloy material of the present invention is preferably arranged so as to contain silver as its main component and zinc. By adding zinc to silver as described above, it is possible to achieve the effects such as the improvement of the heat resistance, adhesion, and plasma resistance. Therefore this silver alloy material is suitable for the manufacturing process of TFT array substrates.

Note that, the silver alloy material of the present invention may further contain another element intentionally added other than silver and zinc. The present invention is based on the principle that the addition of zinc to silver is effective in improving the heat resistance, adhesion, and plasma resistance. Therefore any silver alloy material that is arranged to achieve the effect of the addition of zinc is included in the scope of the present invention, even if the silver alloy material contains an element other than silver and zinc.

Further, when used as a component material of the lines and the like on a TFT array substrate, the silver alloy material of the present invention is most preferably arranged so as to contain silver as its main component and indium. When indium is added to silver as described above, it is possible to characteristically achieve the effects such as the remarkable improvement of the plasma resistance if the indium content is in a ratio of not less than 0.5% by weight with respect to silver. Therefore this silver alloy material is suitable for the manufacturing process of TFT array substrates.

When used as a component material of the lines and the like on a TFT array substrate, the silver alloy material of the present invention is most preferably arranged to contain indium in a ratio of not more than 0.5% by weight with respect to silver in view of low electric resistance. This silver alloy material has an electric resistivity of not more than 2.7 μΩcm, and thus can form the lines having low electric resistance that cannot be achieved by the conventional aluminum lines. This silver alloy material is appropriately used to manufacture a circuit substrate whose lines are especially required to have low electric resistance, as in a liquid crystal display device used for a liquid crystal TV, for example.

As further excellent characteristics, the silver alloy material of the present invention has a high visible light reflectance and retains the reflectance after baked at 200° C. or at 300° C., if the silver alloy material moderately contains indium. This will be explained as follows.

As samples for measurement, a silver film or silver alloy films similar to those used in Comparative Examples and Examples shown in Tables 1 and 2, and an aluminum film similarly produced as Comparative Example 3 for reference were used. Each of these samples was formed into the film having a thickness of about 0.2 μm on a nonalkali substrate whose temperature during the film formation was set to 100° C. The visible light reflectance was measured using a spectrophotometer (U-4100, manufactured by Hitachi Instruments Service Co., Ltd.) with respect to the overall range of visible light whose wavelength is from 380 nm through 780 nm.

The visible light reflectance of the silver alloy film of the present invention will be explained with reference to FIGS. 20 through 25. In FIGS. 20 through 25, the horizontal axis indicates the wavelength of light irradiated on the metal film sample, and the vertical axis indicates the visible light reflectance as a reflectance of the corresponding irradiated light. Each diagram shows the reflectance of the metal film sample at respective points after formed into the film, after baked at 200° C., and after baked at 300° C., so as to show changes in the reflectance caused by the baking. Note that, the baking was performed in such a processing condition that the metal film sample was baked using a clean oven for one hour in a nitrogen atmosphere.

The following will detail the results. First, in Comparative Example 1 (silver) as shown in FIG. 20, the heat resistance was significantly low as described above. Even though the reflectance was high after the film was formed at 100° C., the reflectance was remarkably lowered after the film was baked at 200° C. and at 300° C. Therefore the silver film cannot withstand the manufacturing process that contains the baking step at about 200° C., and cannot be used for a light reflecting film of a reflection type liquid crystal display device, for example.

Next, in Comparative Example 3 (aluminum) as shown in FIG. 21, the light reflectance almost did not change with respect to the aluminum film after formed, after baked at 200° C., and after baked at 300° C. Aluminum has been commonly used for a light reflecting film of a reflection type liquid crystal display device.

FIG. 22 is an example of the silver alloy film of the present invention where the silver alloy film contains indium in an amount of 0.05% by weight with respect to silver. In this case, unlike the results with respect to silver as shown in FIG. 20, the lowering of the reflectance with respect to the film after baked at 200° C. and at 300° C. was remarkably reduced. Further, compared with the aluminum film shown in FIG. 21, the silver alloy film after baked at 200° C. had high reflectance with respect to almost all range of the wavelength. Further, the silver alloy film after baked at 300° C. had high reflectance with respect to an almost overall range except a quite narrow range on the side of short wavelength. This reveals that the silver alloy film of the present Example has high visible light reflectance, and excels as a light reflecting film.

FIG. 23 also shows an example of the silver alloy film of the present invention where the silver alloy film contains indium in an amount of 0.2% by weight with respect to silver. In this case, the results are almost the same as those in Example 7 shown in FIG. 22. The reflectance of the silver alloy film after baked at 200° C. and at 300° C. was not much lowered, and the visible light reflectance as a whole was higher than that of the aluminum film. Therefore the silver alloy film of the present Example is excellent as a light reflecting film.

FIG. 24 shows a case where the silver alloy film contains indium in a ratio of 0.5% by weight with respect to silver. The reflectance of the silver alloy film after baked at 200° C. was more excellent than that of the aluminum film with respect to an almost overall range except a quite narrow range on the side of short wavelength. However, the reflectance of the silver alloy film after baked at 300° C. was lowered especially on the side of short wavelength, and was not superior to the aluminum film. As shown in the present Example, indium should be moderately added to silver, and the reflectance of the silver alloy film is lowered if indium is added too much.

FIG. 25 shows a case where the silver alloy film contains indium in a ratio of 1.6% by weight with respect to silver. In this case, because of the increased indium content, the reflectance was lowered as a whole. Therefore the silver alloy film of the present Example was not superior to the aluminum film.

The foregoing revealed that, if the silver alloy film contains indium in a ratio of not more than 0.5% by weight, the reflectance of the silver alloy film after baked at 200° C. almost does not vary from the reflectance of the silver alloy film after formed, and the reflectance is high with respect to an almost overall range of visible light, compared with the aluminum film. Therefore the silver alloy film as arranged above is suitably used as a light reflecting film.

Further, if the silver alloy film contains indium in a ratio of not more than 0.2% by weight, the lowering of the reflectance of the silver alloy film after baked at 300° C. is reduced, and the reflectance of the silver alloy film is high with respect to an almost overall range of visible light, as in the aluminum film. Therefore the silver alloy film as arranged above is suitably used as a light reflecting film that especially requires heat resistance.

Note that, the silver alloy material of the present invention may further contain another element intentionally added other than silver and indium. The present invention is based on the principle that the addition of indium to silver is most effective in improving the plasma resistance. Therefore any silver alloy material that is arranged to achieve the effect of the addition of indium is included in the scope of the present invention, even if the silver alloy material contains an element other than silver and indium.

The scope of the present invention covers embodiments in which the material contains silver, zinc, and indium, the material contains silver, tin, and indium, and the material contains silver, zinc, and tin.

The silver alloy material of the present invention is suitably used as a material that makes up lines and the like on a TFT array substrate. This TFT array substrate is suitably used for a liquid crystal display device which is an electronic device.

A TFT array substrate and a liquid crystal display device in accordance with the present embodiment will be explained with reference to FIG. 1 through 4.

The liquid crystal display device in accordance with the present embodiment includes a pixel as shown in FIG. 1. Note that, FIG. 1 is a plan view schematically showing an arrangement of a pixel on a TFT array substrate 11 of the liquid crystal display device. Further, FIG. 2 shows a cross-sectional view corresponding to line A-A of FIG. 1.

As shown in FIGS. 1 and 2, the TFT array substrate 11 is arranged so that gate lines 13 and source lines 14 are arranged in a matrix manner on a glass substrate (insulation substrate) 12, and TFTs 15 are provided in the vicinity of areas where the gate lines 13 and the source lines 14 cross. Further, a storage capacitance line 16 is provided between each of two adjacent gate lines 13.

As shown in FIG. 2, a gate electrode 17 branching from the gate line 13, and the storage capacitance line 16 are formed on the glass substrate 12. On the gate electrode 17 and the storage capacitance line 16, a gate insulation layer 18 is formed.

On the gate electrode 17, an amorphous silicon layer 19, an n+ type silicon layer 20, a source electrode 21, and a drain electrode line 22 are formed via the gate insulation layer 18, so that the TFT 15 is formed. Here, the source electrode 21 branches from the source line 14.

The drain electrode line 22 extends from the TFT 15 to a contact hole 23. The function of the drain electrode line 22 is to serve as a drain electrode of the TFT 15, electrically connect the TFT 15 with a pixel electrode 24, and form an electric capacitance with the storage capacitance line 16 at the contact hole 23. Further, on the drain electrode line 22, a passivation layer 25 covering the TFT 15; an interlayer insulation layer 26 for planarization, etc.; and the pixel electrode 24 for applying a voltage to liquid crystal, etc., are formed.

Hereinafter a portion on the glass substrate 12 where the pixels as described above are provided is referred to as a pixel formation area 61, and illustrated in FIG. 4 to be described later.

Further, the liquid crystal display device in accordance with the present embodiment includes a terminal section 28 shown in FIG. 3(a). The terminal section 28 is a connection section for connecting the TFT array substrate 11 with an external circuit substrate, a driver IC, and the like. Note that, FIG. 3(a) is a plan view schematically showing an arrangement of one terminal section on the TFT array substrate 11 of the liquid crystal display device. Further, FIG. 3(b) shows a cross-sectional view corresponding to line B-B of FIG. 3(a).

As shown in FIG. 3(b), the terminal section 28 is arranged so that a terminal line 30, the gate insulation layer 18, and a terminal electrode 29 are sequentially provided in this order on the glass substrate 12. The terminal electrode 29 is provided to improve the electrical connection with the external circuit substrate and the driver IC, for example. The terminal line 30 is connected to the gate line 13, the source line 14, and the like, in the pixel formation area 61.

Hereinafter, portions on the glass substrate 12 where the terminal sections 28 as described above are provided are referred to as terminal section formation areas 62, and illustrated in FIG. 4 to be described below.

FIG. 4 is a plan view of the TFT array substrate 11. The pixel formation area 61 and the terminal section formation areas 62 are arranged on the glass substrate 12 as shown in FIG. 4. The pixel formation area 61 and the terminal section formation areas 62 are provided with many pixels and terminal sections, respectively, as shown in FIGS. 1 through 3.

In the present embodiment, the TFT array substrate 11 is manufactured using pattern formation equipment employing an ink-jet method, for example, which discharges or drops a material for a layer to be formed. As shown in FIG. 5, the pattern formation equipment is provided with a placing table 32 for placing thereon a substrate 31 (corresponding to the glass substrate 12), an ink-jet head 33, an X-direction driving section 34 for moving the ink-jet head 33 in an X direction, and a Y-direction driving section 35 for moving the ink-jet head 33 in a Y direction. The ink-jet head 33 discharges fluid droplets containing wiring material, for example, onto the substrate 31 on the placing table 32.

Further, the pattern formation equipment is provided with an ink supply system 36 for supplying ink to the ink-jet head 33, and a control unit 37 for performing various types of control such as control of the discharging of the ink-jet head 33, and control of the driving of the X-direction driving section 34 and Y-direction driving section 35. The control unit 37 outputs application position information to the X-direction and Y-direction driving sections 34 and 35, and outputs discharging information to a head driver (not shown) of the ink-jet head 33. With this, the ink-jet head 33 operates together with the X-direction and Y-direction driving sections 34 and 35, so as to supply a target amount of the droplets to a target position on the substrate 31.

The ink-jet head 33 may employ a piezo system that uses a piezo actuator, a bubble system by containing a heater within the head, or other system. An amount of ink to be discharged from the ink-jet head 33 can be controlled by control of an applied voltage. Further, the droplet discharging means is not limited to the ink-jet head 33, and may employ any system that can supply droplets, such as a system that simply drops droplets. Further, a system such as an application or immersion system that obtains a predetermined pattern using lyophilic areas and non-lyophilic areas with respect to the wiring formation material may be also employed. Here, the lyophilic areas and non-lyophilic areas have been formed on the substrate beforehand.

Next, a method for manufacturing the TFT array substrate 11 in the liquid crystal display device in accordance with the present embodiment will be explained.

In the present embodiment, the manufacturing method of the TFT array substrate 11 includes a gate line pre-processing step 101, a gate line formation step 102, a gate insulation film and semiconductor film formation step 103, a gate insulation film and semiconductor film processing step 104, a source and drain lines pre-processing step 105, a source and drain lines formation step 106, a channel section processing step 107, a passivation film and interlayer insulation layer formation step 108, a passivation film processing step 109, and a pixel electrode formation step 110.

(Gate Line Pre-Processing Step 101)

In the gate line pre-processing step 101, pre-processing for forming the gate line 13, the gate electrode 17, and the storage capacitance line 16, and the like, is performed. The following will explain this processing with reference to FIGS. 7(a) and 8(a). FIGS. 7(a) and 8(a) are plan view of the glass substrate provided to the TFT array substrate 11.

In the present gate line pre-processing step 101, the processing is performed so as to allow fluid wiring material is to be properly applied to a gate line formation area 41, a gate electrode formation area 42, a storage capacitance line formation area 43, and a terminal line formation area 44 as shown in FIGS. 7(a) and 8(a) when the fluid wiring material is discharged (dropped) from the pattern formation equipment.

This processing roughly includes the following.

First, either wettable or repellent property with respect to the fluid wiring material is imparted onto the substrate (glass substrate 12). Namely, this is hydrophilic and hydrophobic processing (lyophilic and lyophobic processing) for patterning (A) hydrophilic areas (lyophilic areas) where the gate line formation area 41, gate electrode formation area 42, storage capacitance line formation area 43, and terminal line formation area 44 are to be formed and (B) hydrophobic areas (lyophobic areas) where the gate line formation area 41, gate electrode formation area 42, storage capacitance line formation area 43, and terminal line formation area 44 are not to be formed.

Second, guides for regulating the flow of liquid, namely, guides along the gate line formation area 41 and the like are formed.

The hydrophilic and hydrophobic processing is typically photocatalysis processing using titanium dioxide. The processing for forming the guides employs photolithography using a photo resist. Further, the guides or the surface of the substrate may be exposed to plasma into which CF₄ gas and O₂ gas have been introduced, so that either the lyophilic or lyophobic property is imparted to the guides or the surface of the substrate. The resist used here is removed after the lines are formed.

Here, the photocatalysis processing using titanium dioxide is performed as follows. Namely, a mixture of ZONYL FSN (Trade name, manufactured by Dupont), which is a fluorochemical non-ionic surface-active agent, and isopropyl alcohol is coated on the glass substrate 12 of the TFT array substrate 11. Further, a mixture of titanium dioxide fine-particle dispersed in dispersion medium and ethanol is coated as a photocatalyst layer on a mask for the gate line pattern, etc., using a spin-coating method, and then baked at 150° C. Subsequently, using the mask, the glass substrate 12 is exposed for two minutes by irradiation of ultraviolet light having a wavelength of 365 nm at an intensity of 70 mW/cm².

Here, the formation of the lyophilic and lyophobic areas by use of titanium dioxide will be explained with reference to FIGS. 9(a) through 9(d).

FIG. 9(a) shows a state where a film 2 which is made by coating the mixture of ZONYL FSN and isopropyl alcohol is applied to a glass substrate 1 using a spin-coating method or the like.

FIG. 9(b) shows a state where a mask 4 for the gate line pattern, etc., which is provided on a transparent glass substrate 3 is used for the ultraviolet exposing. On a pattern side of the mask 4, the mixture of titanium dioxide fine-particle dispersed in dispersion medium and ethanol has been applied as a photocatalyst layer 5 and heat-treated at 150° C.

After the exposing under the conditions as described above, wettability improves only in a portion 6 that is exposed by ultraviolet, and the portion 6 becomes a lyophilic area, as shown in FIGS. 9(c) and 9(d).

(Gate Line Formation Step 102)

Next, the following will explain the gate line formation step 102 with reference to FIGS. 7(b), 7(c), 8(b), and 8(c).

FIGS. 7(b), 7(c), 8(b), and 8(c) are drawings showing states when the gate line formation step 102 is completed. FIGS. 7(b) and 8(b) are plan views of the glass substrate 12 at the pixel formation area 61 and the terminal section formation area 62, respectively. FIG. 7(c) is a cross-sectional view corresponding to line C-C of FIG. 7(b). FIG. 8(c) is a cross-sectional view corresponding to line D-D of FIG. 8(b).

In the present gate line formation step 102, the fluid wiring material is applied to the lyophilic areas such as the gate line formation area 41, using the pattern formation equipment. The fluid wiring material used here is a material prepared by dispersing into an organic solvent, silver-indium alloy particles coated with organic material. Here, the fluid wiring material is set to contain indium in a ratio of about 5% by weight with respect to silver. The width of the line is set to about 50 μm, and an amount of the wiring material discharged from the ink-jet head 33 is set to 40 pl.

Note that, the ratio of indium to silver in the fluid wiring material is set here so that the wiring made from the fluid wiring material has plasma resistance in view of dry etching in the gate insulation film and semiconductor film processing step 104, channel section processing step 107, and passivation film processing step 109 to be performed later. However, the ratio can be appropriately selected depending on the manufacturing process, the desired performance of the TFT array substrate, and the like.

On the surface that has been subjected to the lyophilic processing, the fluid wiring material discharged from the ink-jet head 33 extends along the gate line formation area 41. Accordingly, application is performed in such a manner that the fluid wiring material is discharged at appropriately adjusted intervals of about 100 μm to 500 μm. After the application, the glass substrate 12 is baked for one hour at 300° C. so that the gate line 13, gate electrode 17, storage capacitance line 16, and terminal line 30 composed of silver and indium are formed.

Here, since the gate line 13 and the like are composed of silver and indium, the gate line 13 and the like have sufficient heat resistance with respect to the 300° C. condition, and do not lose their surface flatness. In contrast, with respect to the same condition, conventional silver significantly loses its surface flatness, and causes a leak between the gate line 13 and the upper layer, resulting in poor quality.

Further, the gate line 13 and the like are directly in contact with the glass substrate 12. Since the gate line 13 and the like are composed of silver and indium in the present example, the gate line 13 and the like have sufficient adhesion to the glass substrate, and do not separate from the glass substrate in the later steps. In contrast, since the conventional silver has low adhesion, the conventional silver separates from the glass substrate in the later steps, resulting in poor quality.

Note that, the temperature for the baking is set to 300° C. here because the processing heat of about 300° C. is to be applied in the following gate insulation film and semiconductor film formation step 103. Therefore the temperature for the baking is not limited to this temperature.

(Gate Insulation Film and Semiconductor Film Formation Step 103)

Next, the following will explain the gate insulation film and semiconductor film formation step 103 with reference to FIGS. 10(a), 10(b), 11(a), and 11(b).

FIGS. 10(a), 10(b), 11(a), and 11(b) are drawings showing states when the gate insulation film and semiconductor film formation step 103 is completed. FIGS. 10(a) and 11(a) are plan views of the glass substrate 12 at the pixel formation area 61 and the terminal section formation area 62, respectively. FIG. 10(b) is a cross-sectional view corresponding to line E-E of FIG. 10(a). FIG. 11(b) is a cross-sectional view corresponding to line F-F of FIG. 11(a).

In the gate insulation film and semiconductor film formation step 103, a gate insulation film 45 to be the gate insulation layer 18, an amorphous silicon film 46 to be the amorphous silicon layer 19, and an n+ type silicon film 47 to be the n+ type silicon layer 20 are continuously formed on the glass substrate 12 that has been subjected to the gate line formation step 102. Here, the gate insulation film 45 is composed of silicon nitride. The gate insulation film 45, the amorphous silicon film 46, and the n+ type silicon film 47 are formed to have thicknesses of 0.3 μm, 0.15 μm, and 0.04 μm, respectively, using a CVD method at a temperature of 300° C.

The heat resistance of the gate line 13 has been improved because of indium that is added to silver as explained in the previous step, so that new grain growth is suppressed. Therefore the surface of the gate line 13 does not become rough under the 300° C. high temperature condition. With this, it is possible to obtain the gate line 13 having a better surface property than the gate line 13 composed of only silver. Accordingly, an electric leak between the gate line 13 and a semiconductor layer 27 or the source electrode 21 to be formed thereon via the gate insulation layer 18 is prevented. This improves the yield of TFT array substrates and stabilizes the characteristics of the TFTs.

(Gate Insulation Film and Semiconductor Film Processing Step 104)

Next, the following will explain the gate insulation film and semiconductor film processing step 104 with reference to FIGS. 12(a), 12(b), 13(a), and 13(b).

FIGS. 12(a), 12(b), 13(a), and 13(b) are drawings showing states when the gate insulation film and semiconductor film processing step 104 is completed. FIGS. 12(a) and 13(a) are plan views of the glass substrate 12 at the pixel formation area 61 and the terminal section formation area 62, respectively. FIG. 12(b) is a cross-sectional view corresponding to line G-G of FIG. 12(a). FIG. 13(b) is a cross-sectional view corresponding to line H-H of FIG. 13(a).

In the gate insulation film and semiconductor film processing step 104, photolithography is used for the processing.

First, the amorphous silicon film 46 and the n+ type silicon film 47 are processed by first photolithography in such a manner that the amorphous silicon film 46 and the n+ type silicon film 47 remains in an island-like manner above the gate electrode 17 in the pixel formation area 61, and do not remain in the terminal section formation area 62. Consequently, the amorphous silicon layer 19, and an n+ type silicon processing film 48 to be the n+ type silicon layer 20 are obtained. Then, etching using a dry etching method is performed while introducing mixed gas of sulfur hexafluoride (SF₆) gas and hydrogen chloride (HCl) gas. Since the gate insulation film 45 covers the entire surface of the substrate until this point, the terminal line 30 and the like are not exposed to the dry etching atmosphere.

Subsequently, the gate insulating film 45 is processed by second photolithography. In the terminal section formation area 62, the gate insulation film 45 is partly etched so that the gate insulation layer 18 and an opening section 49 are obtained. The etching is performed using a dry etching method while introducing mixed gas of CF₄ gas and O₂ gas.

In the dry etching of the gate insulation film 45, the terminal line 30 is exposed to the dry etching atmosphere at the opening section 49 and other electrical connection portions (not shown) formed in the terminal section formation area 62. This is because a dry etching method, though well controllable, cannot be completely free from over etching in actual manufacturing.

Here, if the terminal line 30 is composed of silver as in a conventional technique, the terminal line 30 does not have plasma resistance. Accordingly, the terminal line 30 is significantly etched at the opening section 49, resulting in poor quality. In contrast, in the present embodiment, the terminal line 30 is composed of silver and indium, and a ratio of indium with respect to silver is set to about 5% by weight. Therefore the terminal line 30 has plasma resistance and can withstand the dry etching as described above.

(Source and Drain Lines Pre-Processing Step 105)

Next, the following will explain the source and drain lines pre-processing step 105 with reference to FIG. 14(a). FIG. 14(a) is a plan view showing a state where a line guide 52 for forming the source line 14, source electrode 21, and drain electrode line 22 is formed on the glass substrate that has been subjected to the gate insulation film and semiconductor film processing step 104.

In the source and drain lines formation step 106, a line or the like is not formed in the terminal section formation section 62, thus only the pixel formation area 61 will be explained here.

In the present step, the line guide 52 is formed on portions except an area where the source line 14, the source electrode 21, and the drain electrode line 22 are to be formed (source and drain formation area 53). The line guide 52 is formed using photo resist. Specifically, photo resist is applied onto the glass substrate 12 that has been subjected to the gate insulation film and semiconductor film processing step 104; pre-baked; exposed using a photomask; developed; and post-baked. The line guide 52 is formed here such that a line width of an area where the source line 14 and the source electrode 21 are to be formed is 10 μm, and a line width of an area where the drain electrode line 22 is to be formed is 10 μm to 40 μm. A distance between the source electrode 21 and the drain electrode line 22, namely a length of the channel section 51 of the TFT is set to 4 μm.

Note that, lyophilic processing may be applied to an upper surface of the gate insulation layer 18 using oxygen plasma, and lyophobic processing may be applied to the line guide 52 in such a manner that the line guide 52 is exposed to CF₄ plasma. With this, the wiring material applied by the pattern formation equipment fits the base surface well.

Further, instead of the formation of the line guide 52, the lyophilic and lyophobic processing in accordance with the line or electrode pattern may be performed using the method employing photocatalysis that is used in forming the gate electrode.

(Source and Drain Lines Formation Step 106)

Next, the following will explain the source and drain lines formation step 106 with reference to FIGS. 14(b) and 14(c). FIGS. 14(b) and 14(c) are plan views showing a state when the present source and drain lines formation step 106 is completed. FIG. 14(b) is a plan view of the glass substrate 12 at the pixel formation area 61. FIG. 14(c) is a cross-sectional view corresponding to line I-I of FIG. 14(b).

In the present source and drain lines formation step 106, a line or the like is not formed in the terminal section formation section 62, thus only the pixel formation area 61 will be explained here.

In the present source and drain lines formation step 106, the source line 14, the source electrode 21, and the drain electrode line 22 are formed using the line guide 52 provided in the previous step. The pattern formation equipment as shown in FIG. 5 is used as the application apparatus.

Here, the fluid wiring material used is a material prepared by dispersing into an organic solvent, silver-indium alloy particles coated with organic material. The fluid wiring material here is set to contain indium in a ratio of about 5% by weight with respect to silver.

Note that, the ratio of indium to silver in the fluid wiring material is set here so that the wiring made from the fluid wiring material has plasma resistance in view of dry etching in the channel section processing step 107 and passivation film processing step 109 to be performed later. However, the ratio can be appropriately selected depending on the manufacturing process, the desired performance of the TFT array substrate, and the like.

Here, an amount of the fluid wiring material discharged form the ink-jet head 33 is set to 2 pl. The film is formed to have a thickness of 0.3 μm. A temperature for the baking is 200° C., which is lower than 300° C. at which the amorphous silicon film 46 and the like are formed. The line guide 52 is removed using organic solvent.

(Channel Section Processing Step 107)

Next, the following will explain the channel section processing step 107 with reference to FIG. 15. FIG. 15 is a plan view showing a state when the present channel section processing step 107 is completed, and a cross-sectional view corresponding to line I-I of FIG. 14(b).

In the channel section processing step 107, the channel section 51 of the TFT is processed. The processing is performed by dry etching using chlorine gas. Here, photolithography is not newly performed, and the patterns of the source electrode 21 and the drain electrode line 22 are used for the processing.

In the present embodiment, the pattern formation equipment such as an ink-jet apparatus is used in the previous step. Since the source line 14, the source electrode 21, and the drain electrode line 22 are formed in this manner, it is impossible to leave the resist on the source line 14, the source electrode 21, and the drain electrode line 22 in terms of the process. Therefore, in the channel section processing step 107, the channel section 51 is processed using the source line 14 and the like as masks. Accordingly, the source line 14 and the like are exposed to the dry etching atmosphere for a long time throughout the etching.

In other words, if the pattern formation equipment such as an ink-jet apparatus is used, in particular, the source line 14 and the like are required to have high resistance to a dry etching atmosphere (plasma resistance).

The conventional source line 14 and the like composed of only silver do not have plasma resistance, and thus most of the lines are etched. Consequently, the lines cannot attain desired conductivity, resulting in poor quality. In contrast, in the present embodiment, the source line 14 and the like are composed of silver and indium, and a ratio of indium with respect to silver is set to about 5% by weight. Therefore the source line 14 and the like have plasma resistance and can withstand the dry etching.

As described above, the wiring material of the present invention composed of silver and indium has high plasma resistance, thereby facilitating the method for using pattern formation equipment to manufacture a TFT array substrate which is conventionally difficult to be realized.

(Passivation Film and Interlayer Insulation Layer Formation Step 108)

Next, the following will explain the passivation film and interlayer insulation layer formation step 108 with reference to FIGS. 16(a), 16(b), 17(a), and 17(b). FIGS. 16(a), 16(b), 17(a), and 17(b) are drawings showing states when the present passivation film and interlayer insulation layer formation step 108 is completed. FIGS. 16(a) and 17(a) are plan views of the glass substrate 12 at the pixel formation area 61 and the terminal section formation area 62, respectively. FIG. 16(b) is a cross-sectional view corresponding to line J-J of FIG. 16(a). FIG. 17(b) is a cross-sectional view corresponding to line K-K of FIG. 17(a).

In the present passivation film and interlayer insulation layer formation step 108, a silicon nitride film 55 is formed by a CVD method on the glass substrate 12 that has been subjected to the previous step. Here, the substrate temperature is set to 200° C.

Next, photosensitive acrylic resin material is applied onto an upper surface of the silicon nitride film 55. Then, the applied photosensitive acrylic resin material is exposed using a mask, developed, and baked. With this, the interlayer insulation layer 26 having a predetermined pattern is obtained. Here, an opening section 56 is provided at a portion where the drain electrode line 22 overlaps the storage capacitance line 16. On the other hand, the interlayer insulation layer 26 is not formed in the terminal section formation area 62.

(Passivation Film Processing Step 109)

Next, the following will explain the passivation film processing step 109 with reference to FIGS. 18(a) and 18(b). FIGS. 18(a) and 18(b) are drawings showing states when the present passivation film processing step 109 is completed. FIG. 18(a) is a cross-sectional view corresponding to line J-J of FIG. 16(a). FIG. 18(b) is a cross-sectional view corresponding to line K-K of FIG. 17(a).

In the present passivation film processing step 109, the silicon nitride film 55 formed in the passivation film and interlayer insulation layer formation step 108 is processed using the pattern of the interlayer insulation layer 26. In the pixel formation area 61, the silicon nitride film 55 is etched at a portion directly under the opening section 56, so that the passivation layer 25 and the contact hole 23 are obtained. On the other hand, in the terminal section formation area 62, the silicon nitride film 55 over the entire surface is etched and removed. Here, the etching is performed using a dry etching method while introducing mixed gas of CF₄ gas and O₂ gas.

In the dry etching of the silicon nitride film 55, a part of the drain electrode line 22 and terminal line 30 are exposed to the dry etching atmosphere at the contact hole 23 and the opening section 49 formed in the terminal section 28. This is because a dry etching method, though well controllable, cannot be completely free from over etching in actual manufacturing.

Silver in the conventional technique does not have plasma resistance. Therefore if the drain electrode line 22 and terminal line 30 are composed of silver, the part of the drain electrode line 22 and terminal line 30 are significantly etched, resulting in poor quality. In contrast, in the present embodiment, the drain electrode line 22 and terminal line 30 are composed of silver and indium, and a ratio of indium with respect to silver is set to about 5% by weight. Therefore the drain electrode line 22 and terminal line 30 have plasma resistance and can withstand the dry etching as described above.

(Pixel Electrode Formation Step 110)

In this final step, an ITO (indium tin oxide) film to be the pixel electrode 24 and terminal electrode 29 are formed by a sputtering method. Here the substrate temperature is set to 200° C. Then, the ITO film is patterned using photolithography, so that the TFT array substrate 11 as shown in FIGS. 1, 2, 3(a), 3(b), and 4 is obtained.

As described above, the material of the present invention has excellent adhesion to a glass substrate, which cannot be achieved by the conventional material made of only silver. Therefore the material of the present invention can withstand the series of manufacturing process without causing a defect due to the separation of the gate line or the like from the substrate.

Further, the material of the present invention has excellent heat resistance that cannot be achieved by the conventional material made of only silver. With this, it is possible to obtain the gate line 13, storage capacitance line 16, gate electrode 17, and the like, having good surface property such that the surfaces of the lines do not become rough even if the substrate is exposed under the 300° C. high temperature condition as in the present example. Accordingly, an electric leak between the gate line 13, storage capacitance line 16, gate electrode 17, or the like, and the source line 14, semiconductor layer 27, source electrode 21, or the like, to be formed thereon via the gate insulation layer 18 is prevented. This improves the yield of TFT array substrates and stabilizes the characteristics of the TFTs.

Above all, the high plasma resistance provided to the material of the present invention enables the manufacturing process as described above.

In the present embodiment, dry etching is carried out in a total of three steps, namely, the etching of the gate insulation film 45 in the gate insulation film and semiconductor film processing step 104, etching of the n+ silicon processing film 48 in the channel section processing step 107, and etching of the silicon nitride film in the passivation film processing step 109. Here, if the lines, electrodes, and the like, are formed using only silver as in the conventional technique, the lines, electrodes, and the like, are etched due to over etching or etched when used as etching masks for other films, thus resulting in poor quality. In contrast, the wiring material of the present invention, as in the present embodiment, has excellent plasma resistance, thereby causing no defect.

As described above, dry etching is used many times in manufacturing the TFT array substrate. Accordingly, high dry etching resistance (plasma resistance) is required for the material that composes the lines, electrodes, and the like. The material mainly consisting of silver and containing indium as in the present invention has high plasma resistance, and extremely excels as a material for composing the lines, electrodes, and the like, on the TFT array substrate, in particular.

Further, the material of the present invention is especially effective in a case as in the present embodiment where the source line 14, source electrode 21, and the like, are plotted and formed using pattern formation equipment employing a system such as an ink-jet method. In such a case, the source line 14 and the like are used as etching masks for forming the n+ silicon film 20, and are exposed to the dry etching atmosphere throughout the etching. Therefore it is difficult to apply this process to the conventional source line 14 and the like composed of only silver. In contrast, use of the material of the present invention enables the manufacturing of a TFT array substrate using such pattern formation equipment.

As described above, the silver alloy material of the present invention is particularly suitable for the manufacturing process using the application apparatus such as an ink-jet apparatus, and beneficially used when contained in fluid wiring material. Note that, the silver alloy material of the present invention is also beneficially used in a manufacturing method that does not use the pattern formation equipment, as described later.

The present embodiment employs a six-mask process in which an exposing process using a photomask and a developing process are performed in a total of six times. A five-mask process is also widely used to manufacture TFT array substrates at lower cost. In this case, the easiest method without using halftone exposure, or the like, is to form the gate insulation layer 18 and the passivation layer 25 by consecutively etching the gate insulation film 45 and the silicon nitride film 55. However, in this case, the revealed portion of the drain electrode line 22, in particular, is exposed to the dry etching atmosphere for a long time, and has to withstand the harsh process condition.

In this respect, the substrate during the etching will be examined. First, during the etching of the silicon nitride film 55, no problem occurs because the entire surface of the line is covered with the film. However, during the etching of the gate insulation film 45, the revealed portion of the drain electrode line that is generated at the contact hole 23, for example, is directly exposed to the dry etching atmosphere constantly throughout the etching. This is a very long and harsh process condition.

Therefore, in the five-mask process as described above, high plasma resistance is especially required for the drain electrode line 22. The silver alloy material of the present invention, typified by the silver alloy material containing silver and indium, has high plasma resistance. Therefore the silver alloy material of the present invention can be used in the five-mask process, and has a broad usable range.

Note that, the present embodiment uses the six-mask process and forms the terminal line 30 in the step in which the gate line 13 and the like are formed, but the scope of the present invention is not limited to this. In most of the current manufacturing methods in which a silicon nitride film to be the gate insulation layer or passivation layer 25 are entirely formed on a substrate and then partly removed, a portion of the film should be removed for electrical connection. Accordingly, the electrodes, lines, or the like, provided under the removed portion of the silicon nitride film inevitably require plasma resistance with respect to over etching. The present invention provides a material having excellent plasma resistance, and has an excellent effect on the manufacturing process of these TFT array substrates.

In the present embodiment, the fluid wiring material used is a material prepared by dispersing into an organic solvent, silver-indium alloy particles coated with organic material. The fluid wiring material here is set to contain indium in a ratio of about 5% by weight with respect to silver. However, the ratio can be appropriately selected depending on the manufacturing process, the desired performance of the TFT array substrate, and the like.

Further, the form of the fluid wiring material is not limited to the form that contains silver and indium as silver-indium alloy particles. The form may be such that silver particles and indium particles are separately produced, and then dispersed in a solvent independently from each other. Further, the form of silver and indium is not limited to the particles, and may be silver or indium metal compound contained in the solvent.

In the present embodiment, the silver alloy material containing silver and indium is used to form the lines, electrodes, and the like, such as the source line 14, gate line 13, and the like, but the material is not limited to this. The silver alloy material containing silver and zinc may be used instead. Further, the gate line 13 and the like may be formed using the silver alloy material that is arranged to contain silver and at least one element selected from the group consisting of tin, zinc, lead, bismuth, indium, and gallium. Further, in addition to these elements, the silver alloy material may be arranged to contain at least an element selected from the group consisting of aluminum, copper, nickel, gold, platinum, palladium, cobalt, rhodium, iridium, ruthenium, osmium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, and neodymium.

[Second Embodiment]

The following will explain another embodiment of the present invention with reference to FIGS. 6, 19(a), and 19(b).

In First Embodiment, the pattern formation equipment employing an ink-jet method, for example, is used in the gate line formation step 102 and the source and drain lines formation step 106.

A TFT array substrate 71 in accordance with the present embodiment is produced in a manner as shown in the process flow chart of FIG. 6 as in First Embodiment, except that in the gate line formation step 102, two or more types of fluid wiring materials are used to form the lines and the like having different compositions within the substrate (separate application).

Note that, constituent elements substantially having the same function as those used in First Embodiment are given the same reference symbols, thus their explanation will be omitted here.

FIGS. 19(a) and 19(b) show a TFT array substrate 71 in accordance with the present embodiment. FIG. 19(a) is a plan view of the terminal formation area 62 of the TFT array substrate 71, and FIG. 19(b) is a cross-sectional view corresponding to line L-L of FIG. 19(a). A pixel portion formed in the pixel formation area 61 shown in FIG. 4 is arranged as the pixel portion in First Embodiment. As shown in FIGS. 19(a) and 19(b), in the TFT array substrate 71 of the present embodiment, a terminal line 72 contacts and electrically connects a terminal line connection section 73.

Since the terminal line 72 is covered with the gate insulation layer 18, the terminal line 72 only needs to have heat resistance and adhesion to a glass substrate among the process resistance. The terminal line 72 does not require plasma resistance because the terminal line 72 is not exposed to a dry etching atmosphere. On the other hand, the electric resistance of the terminal line 72 should be as low as possible, if the manufactured circuit substrate is to be used for a large-sized liquid crystal display device, in particular. Accordingly, the terminal line 72 is arranged to contain 3% of indium by weight with respect to silver and have an electric resistivity of about 6 μΩcm. Further, for the same reason, the gate line 13, the gate electrode 17, and the storage capacitance line 16 in the pixel formation area 61 are also arranged to contain 3% of indium by weight with respect to silver so as to have lower electric resistance.

In contrast, the terminal line connection section 73 is exposed to a dry etching atmosphere due to over etching in the etching step for electrical connection. Accordingly, the terminal line connection section 73 is arranged to contain 10% of indium by weight with respect to silver, in view of emphasis on plasma resistance. Since the terminal line connection section 73 is much shorter than the gate line 13, source line 14, and terminal line 72 on the TFT array substrate, the terminal line connection section 73 can have a larger electric resistivity than the other lines.

Of course, both of the terminal line 72 and the terminal line connection section 73 may be arranged in the same manner as in First Embodiment, namely, may be arranged to contain 5% of indium by weight with respect to silver. However, by performing the separate application in response to each performance required for each of the parts, it is possible to form the lines, electrodes, and the like, having lower electric resistance as a whole, thereby realizing a circuit substrate having a larger size, a display device having a larger size, and the like.

The following will explain a manufacturing method of the present embodiment.

As explained above, the TFT array substrate 71 of the present embodiment is manufactured in a manner similar to that in First Embodiment, except that the fluid wiring materials are separately applied in the gate line formation step 102. The separate application can be realized if the pattern formation equipment as shown in FIG. 5 is capable to discharge at least two types of fluid wiring materials. Specifically, the pattern formation equipment may be provided with at least two ink-jet heads 33; or the ink-jet head 33, as well as the ink supply system 36, the control unit 37, and discharging position information, and the like, may be set to be capable of dealing with two types of fluid wiring materials.

The pattern formation equipment as described above is used to discharge in a manner as in First Embodiment, two types of fluid wiring materials respectively containing different amounts of indium with respect to silver. A fluid wiring material that contains indium in an amount of 3% by weight with respect to silver when formed into the terminal line 72 is discharged to a portion to be the terminal line 72. On the other hand, a fluid wiring material that contains indium in an amount of 10% by weight with respect to silver when formed into the terminal line connection section 73 is discharged to a portion to be the terminal line connection section 73. The fluid wiring material the same as that of the terminal line 72 is discharged to portions where the gate line 13, the gate electrode 17, and the storage capacitance line 16 are to be formed in the pixel formation area 61. After discharged, the fluid wiring materials are baked for one hour at 300° C. as in First Embodiment. With this, the predetermined terminal line 72, terminal line connection section 73, and the like, are obtained.

In the present embodiment, it is important that (A) the pattern formation equipment employing a system such as an ink-jet method can carry out separate application to the surface of the substrate, (B) different parts of the lines and the like formed in the same step respectively require different plasma resistance or conductivity, and (C) the relationship between the indium content, conductivity, and process resistance of the material of the present invention is combined well. With this, it is possible to manufacture a large-sized TFT array substrate that can be easily manufactured and that has good electric properties.

Note that, in the present embodiment, the terminal line 72 and the terminal line connection section 73 are separated by a boundary 74 that separates the materials having different contents of indium, but the present invention is not limited to this. The indium content in the materials may gradually change in the vicinity of the boundary. This gradual boundary may be formed in such a manner that the fluid wiring materials mix with each other by themselves, or intentionally mixed with each other by alternate discharging of the two types of fluid wiring materials. Further, the position of the boundary 74 is not limited to that shown in FIG. 19, and may be slightly varied provided that the foregoing effects are substantially achieved.

Of course, an important point of the present embodiment is to provide the lines, electrodes, and the like, containing an increased amount of indium at portions which are required in the TFT array substrate 71 and which are exposed to a dry etching atmosphere in the manufacturing process.

As described above, even if the silver alloy material of the present invention contains a comparatively low amount of indium, namely, 1% by weight or 3% by weight, for example, with respect to silver, the silver alloy material can be applied to many manufacturing processes if the separate application is performed. Therefore the silver alloy material can be appropriately used as a material having especially low electric resistance for composing the lines and electrodes such as the gate line 13.

Further, the form of the fluid wiring material of the present embodiment is not limited to the form that contains silver and indium as silver-indium alloy particles. The form may be such that silver particles and indium particles are separately produced, and then dispersed in a solvent independently from each other. Further, the form of silver and indium is not limited to the particles, and may be silver or indium metal compound contained in the solvent.

Note that, in the present embodiment, the silver alloy material containing silver and indium is used to form the gate line 13 and the like, but the material is not limited to this. The silver alloy material containing silver and zinc may be used instead. The gate line 13 and the like may be formed using the silver alloy material that is arranged to contain silver and at least one element selected from the group consisting of tin, zinc, lead, bismuth, indium, and gallium. Further, in addition to these elements, the silver alloy material may be arranged to contain at least an element selected from the group consisting of aluminum, copper, nickel, gold, platinum, palladium, cobalt, rhodium, iridium, ruthenium, osmium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, and neodymium.

Further, the silver alloy material having different compositions, such as silver alloy material containing indium, silver alloy material containing zinc, etc., may be respectively used at different portions on the TFT array substrate 71.

[Third Embodiment]

The following will explain a further embodiment of the present invention.

In Second Embodiment, the pattern formation equipment typified by ink-jet pattern formation equipment is used in the gate line formation step 102 to separately apply wiring materials having different compositions onto the TFT array substrate 71.

Note that, constituent elements substantially having the same function as those used in First and Second Embodiments are given the same reference symbols, thus their explanation will be omitted here.

In the present embodiment, the separate application of the wiring materials having different compositions is performed in the source and drain lines formation step 106, instead of the gate line formation step 102. Here, the wiring materials are arranged such that an amount of indium with respect to silver is 3% by weight in the source electrode 21 and source line 14, and 10% by weight in the drain electrode line 22, for example.

Further, within the drain electrode line 22, wiring material containing 3% of indium by weight with respect to silver and wiring material containing 10% of indium by weight with respect to silver may be separately applied in such a manner that plasma resistance increases in the vicinity of the contact hole 23. Similarly, such separate application may be performed at any portion on the TFT array substrate of the present embodiment.

Further, the form of the fluid wiring material of the present embodiment is not limited to the form that contains silver and indium as silver-indium alloy particles as in Second Embodiment. The form may be such that silver particles and indium particles are separately produced, and then dispersed in a solvent independently from each other. Further, the form of silver and indium is not limited to the particles, and may be silver or indium metal compound contained in the solvent.

Note that, the wiring material used in the present embodiment is not limited to the material composed of silver and indium, and may be silver alloy material containing silver and zinc, as explained in Second Embodiment. Further, the source line 14 and the like may be formed using the silver alloy material that is arranged to contain silver and at least one element selected from the group consisting of tin, zinc, lead, bismuth, indium, and gallium. Further, in addition to these elements, the silver alloy material may be arranged to contain at least an element selected from the group consisting of aluminum, copper, nickel, gold, platinum, palladium, cobalt, rhodium, iridium, ruthenium, osmium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, and neodymium.

Further, the silver alloy material having different compositions, such as silver alloy material containing indium, silver alloy material containing zinc, etc., may be respectively used at different portions on the TFT array substrate 71.

Note that, Second and Third Embodiments may be carried out in combination. In other words, the separate application may be performed in both the gate line formation step 102 and the source and drain lines formation step 106.

In First through Third Embodiments of the present invention, the pattern formation equipment employing a system such as an ink-jet method which discharges droplets of fluid wiring material is used. However, the silver alloy material of the present invention also can be beneficially used in a case where such pattern formation equipment is not used. In this case, the TFT array substrate is manufactured in such a manner that the most common conventional method that uses a sputtering or an evaporation method and photolithography is performed in steps corresponding to the steps that use the pattern formation equipment. In this case, instead of the fluid wiring material, a sputtering target, an evaporation source for the evaporation, or the like, is used to obtain the lines, electrodes, and the like, that are formed with the silver alloy composition of the present invention. The silver alloy material of the present invention in this case can be equivalently used beneficially as a material having excellent process resistance such as heat resistance, adhesion, and plasma resistance, as well as low electric resistance.

Note that, the silver alloy material of the present invention can be also used beneficially as a layer in a multilayer wiring structure in which materials are layered in two or more layers. For example, after baked at 300° C., the layer made of the silver alloy material of the present invention does not lose its surface flatness, unlike the material composed of only silver. Further, if the silver alloy material contains indium in a comparatively large amount, namely, 5% by weight or 10% by weight, for example, with respect to silver, the silver alloy material has sufficient plasma resistance, and can be effectively used as a protection metal layer for protecting the lines of a layer under the protection metal layer. Further, the layer made of the silver alloy material of the present invention may be used in First Embodiment as all of or part of the source electrode 21 and drain electrode line 22 which directly contact the semiconductor layer 27 for electrical connection. Here, the layer has equivalently excellent heat resistance and adhesion, and is beneficially used in the manufacturing process of the TFT array substrate.

Further, the silver alloy material of the present invention may be used for a light reflective electrode on a TFT array substrate in a reflection type TFT liquid crystal display device, etc. In this case, due to the excellent heat resistance of the silver alloy material of the present invention, the light reflective electrode does not lose its surface flatness after baked at 300° C., for example, unlike the material composed of only silver. Therefore the light reflective electrode can maintain sufficient light reflectance without causing undesigned light scattering. With this, it is possible to fully exhibit the characteristics of the TFT array substrate.

Further, if the silver alloy material of the present invention contains indium in a ratio of not more than 0.5% by weight with respect to silver, in particular, the silver alloy material has an electric resistivity of not more than 2.7 μΩcm, and can beneficially form the lines having low electric resistance that cannot be achieved by conventional aluminum lines. However, because of the low indium content, this silver alloy material does not have sufficient plasma resistance, and generally requires another metal film to be layered thereon. Further, because of the low indium content, the silver alloy material does not have sufficient adhesion to the substrate, and may require pre-processing and the like.

[Fourth Embodiment]

The following will explain yet another embodiment of the present invention.

Note that, constituent elements substantially having the same function as those used in First through Third Embodiments are given the same reference symbols, thus their explanation will be omitted here.

In Second Embodiment, wiring materials respectively having different compositions are separately applied onto the TFT array substrate 71 in the gate line formation step 102 using the pattern formation equipment typified by ink-jet pattern formation equipment. On the other hand, in Third Embodiment, the separate application of the wiring materials having different compositions is performed in the source and drain lines formation step 106.

In the present embodiment, the lines and the like are formed using a sputtering method in the gate line formation step 102, and these lines are arranged so that the silver alloy material of the present invention and titanium are layered.

FIGS. 26(a), 26(b), 27(a), and 27(b) are drawings showing states when the gate line formation step 102 is completed. FIGS. 26(a) and 27(a) are plan views of the glass substrate 12 at the pixel formation area 61 and the terminal section formation area 62, respectively. FIG. 26(b) is a cross-sectional view corresponding to line M-M of FIG. 26(a). FIG. 27(b) is a cross-sectional view corresponding to line N-N of FIG. 27(a).

In FIGS. 26(a), 26(b), 27(a), and 27(b), a gate line 80, a gate electrode 81, a storage capacitance line 82, and a terminal line 83 have the same multilayer structure composed of two layers. Layers 80 a, 81 a, 82 a, and 83 a on the side close to the glass substrate 12 are composed of the silver alloy of the present invention that contains indium in an amount of 0.2% by weight with respect to silver. Layers 80 b, 81 b, 82 b, and 83 b on the upper side are composed of titanium. The thickness of each of the layers 80 a, 81 a, 82 a, 83 a, 80 b, 81 b, 82 b, and 83 b is set to 0.2 μm.

In the present embodiment, the layers 80 a, 81 a, 82 a, and 83 a that are close to the glass substrate 12 are composed of alloy made of silver and indium, and thus have heat resistance. With this, the gate line 80 and the like are not adversely affected by the baking at about 300° C. in the steps to be performed later. If the gate line 80 and the like are composed of only silver as in the conventional technique, the surfaces of the gate line 80 and the like become remarkably rough with respect to the same condition because the gate line 80 and the like lack heat resistance, and a leak between upper and lower layers occurs.

Further, if the silver alloy material of the present invention contains indium in a ratio of not more than 0.5% by weight with respect to silver, the silver alloy material has an electric resistivity of not more than 2.7 μΩcm as described above, and can beneficially form the lines having low electric resistance that cannot be achieved by conventional aluminum lines. In the present example, the electric resistivity is very low, namely, 2.3 μΩcm. Therefore the silver alloy material of the present invention is effectively used for the lines that are especially required to have low electric resistance, as in a liquid crystal display device used for a liquid crystal TV, for example.

The following will explain a method for forming the gate line 80 and the like in the present embodiment. Here, the pattern formation equipment typified by ink-jet pattern formation equipment is not used in the gate line formation step 102. Thus, a step corresponding to the gate line pre-processing step 101 is not performed.

First, silver alloy film containing indium in an amount of 0.2% by weight with respect to silver is formed to have a thickness of 0.2 μm on the glass substrate 12 by a sputtering method. Here, an alloy target prepared by dissolving indium into silver is used as the sputtering target.

Next, titanium is continuously formed into films in a vacuum using a sputtering method. The thus obtained films are processed by photolithography, so that the gate line and the like as shown in FIGS. 26(a), 26(b), 27(a), and 27(b) are obtained. A dry etching method is used for the etching.

The terminal line 83 and the like require plasma resistance in view of the steps to be performed later. In the present embodiment, the plasma resistance is achieved by titanium of the upper layers.

As described above, the silver alloy material of the present invention may be used as a layer in a multilayer wiring structure. By setting an amount of indium with respect to silver to be not more than 0.5% by weight, it is possible to realize the lines having low electric resistance that cannot be realized by conventional aluminum lines.

Note that, in the foregoing formation method, the silver alloy film of the present invention is formed into a film directly on the glass substrate 12. But, if the adhesion to the substrate is not sufficiently obtained in this method, an intermediate layer made of metal, etc., may be provided between the glass substrate and the silver alloy film; or the surface of the glass substrate may be subjected to plasma treatment, chemical treatment, or other treatment in order to achieve the adhesion.

In the present invention, the material of the layers 80 b, 81 b, 82 b, and 83 b on the upper side is not limited to titanium, and may be chromium, molybdenum, tantalum, and tungsten; a material in which chromium, molybdenum, tantalum, or tungsten contains nitrogen and/or oxygen; or metal oxide such as ITO (indium tin oxide). The gate line 80 and the like may be formed in such a manner that fluid wiring material is applied and layered as in First Embodiment. As another example, the gate line 80 and the like may be formed by using an evaporation method using an evaporation source composed of silver and indium.

In the present embodiment, the lines are formed in the gate line formation step 102 using films composed of the silver alloy of the present invention and titanium. As another embodiment of the present invention, the lines composed of multilayer film may be similarly formed in the source and drain lines formation step 106. In this case, the alloy composed of silver and indium has heat resistance, and is not adversely affected by the baking in the steps to be performed later.

In this case, by setting an amount of indium with respect to silver to be not more than 0.5% by weight, it is equivalently possible to realize the lines having low electric resistance that cannot be realized by conventional aluminum lines.

[Fifth Embodiment]

Further, the silver alloy material of the present invention may be used for a light reflective electrode on a TFT array substrate in a reflection type TFT liquid crystal display device, etc. In this case, due to the excellent heat resistance of the silver alloy material of the present invention, the light reflective electrode does not lose its surface flatness after baked at 300° C., for example, unlike the material composed of only silver. Therefore the light reflective electrode can maintain sufficient light reflectance without causing undesigned light scattering. With this, it is possible to fully exhibit the characteristics of the TFT array substrate.

In this case, the silver alloy material preferably contains indium in an amount of 0.5% by weight with respect to silver, and more preferably contains indium in an amount of 0.2% by weight with respect to silver.

The following will explain still another embodiment of the present invention.

Note that, constituent elements substantially having the same function as those used in First through Fourth Embodiments are given the same reference symbols, thus their explanation will be omitted here.

As shown in First Embodiment of the present invention, among the silver alloy materials of the present invention, a film formed with the silver alloy material that contains indium in an amount of not more than 0.5% by weight with respect to silver retains high visible light reflectance after baked at 200° C. More preferably, a film formed with the silver alloy material that contains indium in an amount of not more than 0.2% by weight with respect to silver retains high visible light reflectance after baked at 300° C. Therefore these silver alloy materials are suitably used for a light reflecting film.

In the present embodiment, light reflective electrodes are formed using the silver alloy material containing indium in an amount of 0.2% by weight with respect to silver. A large number of the light reflective electrodes are formed on a TFT array substrate. The following will explain this.

A reflection type TFT liquid crystal display device in accordance with the present embodiment includes a pixel shown in FIG. 28. Note that, FIG. 28 is a plan view schematically showing an arrangement of a pixel in a TFT array substrate 91 of the reflection type TFT liquid crystal display device. Further, FIG. 29 shows a cross-sectional view corresponding to line O-O of FIG. 28. One of the differences between the liquid crystal display device of the present embodiment and the liquid crystal display device as in First Embodiment of the present invention is that the liquid crystal display device of the present embodiment is provided with light reflective electrodes 84. The light reflective electrodes function as electrodes for applying voltages to a liquid crystal layer (not shown) provided to the liquid crystal display device, and as electrodes for achieving image display by reflecting or scattering external light that entered the liquid crystal display device.

Further, the liquid crystal display device in accordance with the present embodiment includes a terminal section 28 shown in FIG. 30(a). The terminal section 28 is a connection section for connecting the TFT array substrate 91 with an external circuit substrate, a driver IC, and the like. Note that, FIG. 30(a) is a plan view schematically showing an arrangement of one terminal section in the TFT array substrate 91 of the liquid crystal display device. Further, FIG. 30(b) shows a cross-sectional view corresponding to line P-P of FIG. 30(a).

As shown in FIG. 30(b), the terminal section 28 is arranged so that the terminal line 30, the gate insulation layer 18, and a terminal electrode 85 are sequentially provided on the glass substrate 12. Unlike the terminal electrode as in First Embodiment of the present invention, the terminal electrode 85 is formed using silver alloy material containing indium in an amount of 0.2% by weight with respect to silver.

Note that, in the reflection type TFT liquid crystal display, the interlayer insulation layer 26 may be provided with uneven surface for controlling the reflection and scattering of external light. But the uneven surface does not have an influence on the content of the present invention, thus their description is omitted here.

For manufacturing the reflection type TFT liquid crystal display device, it is necessary to bake the substrate at about 160° C. to 200° C. after the light reflective electrodes are formed thereon. This baking is performed to form a liquid crystal orientation film (not shown), for example. Accordingly, the light reflective electrodes 84 require heat resistance.

Silver used in a conventional technique remarkably lacks heat resistance, and cannot be used as the light reflective electrodes because silver becomes easily clouded during the baking. If the silver alloy material of the present invention contains indium in an amount of 0.2% by weight with respect to silver, for example, the silver alloy material can withstand the baking, and can achieve a higher visible light reflectance as a whole than aluminum which is conventionally employed. Therefore by employing the silver alloy material of the present invention, the reflection type TFT liquid crystal display device can achieve brighter display than the conventional reflection type TFT liquid crystal display device that employs aluminum, thereby improving the display performance.

The following will explain a method for manufacturing the light reflective electrode 84 and the terminal electrode 85 in accordance with the present embodiment.

In the present embodiment, the film is formed on the substrate that has been subjected to the passivation film processing step 109 as shown in FIGS. 18(a) and 18(b). The film is formed at a temperature of 100° C. using a sputtering method. Here, an alloy target prepared by dissolving indium into silver is used as the sputtering target. In this manner, the silver alloy film containing 0.2% of indium by weight with respect to silver is formed to have a thickness of 0.2 μm.

The thus obtained silver alloy film is processed into a predetermined pattern using photolithography, so that the light reflective electrode 84 and the terminal electrode 85 are obtained as shown in FIGS. 28 through 30. The etching is performed by a wet etching method using an etching liquid that contains acetic acid, phosphoric acid, or nitric acid.

As described above, among the silver alloy materials of the present invention, a film formed with the silver alloy material that contains indium in an amount of not more than 0.5% by weight with respect to silver retains high visible light reflectance after baked at 200° C., and has more excellent light reflectance as a whole than that of aluminum. Therefore this film is industrially very useful. More preferably, a film formed with the silver alloy material that contains indium in an amount of not more than 0.2% by weight with respect to silver retains high visible light reflectance after baked at 300° C. Therefore this film can withstand harsher manufacturing conditions.

Note that, the manufacturing method of the light reflective electrode 84 and the terminal electrode 85 is not limited to the method as described above. The light reflective electrode 84 and the terminal electrode 85 may be formed in such a manner that fluid wiring material is applied as in First Embodiment, or in such a manner that the film is formed and processed by an evaporation method using an evaporation source composed of silver and indium.

Note that, the silver alloy film of the present invention is formed into a film directly on the interlayer insulation layer 26 in the foregoing formation method. But, if the adhesion to the interlayer insulation layer is not sufficiently obtained in this method, an intermediate layer made of metal, etc., may be provided between the interlayer insulation layer and the silver alloy film, or the surface of the interlayer insulation layer may be subject to plasma treatment, chemical treatment, or other treatment in order to achieve the adhesion.

Further, the silver alloy material of the present invention may be also used for a bus electrode and a data electrode on a glass substrate that constitutes a PDP (plasma display panel). These electrodes are provided on a front side glass substrate or back side glass substrate so as to drive the PDP. These electrodes are conventionally arranged to have layer(s) of silver, chromium/copper/chromium, or aluminum/chromium. Since copper and aluminum have weak adhesion to a glass substrate; a chromium layer needs to be sandwiched between the glass substrate and the copper or aluminum layer. On the other hand, silver which is conventionally used has a problem in heat resistance, and when baked at high temperature, the crystal grains of silver grow. Therefore silver is difficult to be used as the material for the bus and data electrodes.

In contrast, the silver alloy material of the present invention has excellent heat resistance and adhesion to a glass substrate. Therefore the silver alloy material of the present invention can replace the conventional material such as silver, and can be beneficially used as the bus electrode and the data electrode.

[Sixth Embodiment]

The following will explain yet another embodiment of the present invention.

The present embodiment will explain a TFT array substrate and a liquid crystal display device in which the silver alloy material as explained in the foregoing embodiments is used as the wiring material of lines (including electrodes) on the TFT array substrate which is a kind of a circuit substrate.

The silver alloy material used here is a material which composes lines and/or electrodes formed on an insulation substrate such as a glass substrate, and contains silver as a main component and at least one element selected from the group consisting of tin, zinc, lead, bismuth, indium, and gallium.

With the silver alloy material as arranged above, it is possible to form lines or electrodes having low electric resistance, as well as high process resistance such as heat resistance, adhesion to the glass substrate, and plasma resistance.

A TFT array substrate and a liquid crystal display device in accordance with the present embodiment will be explained with reference to FIGS. 1, 2, 4, and 31.

The liquid crystal display device in accordance with the present embodiment includes a pixel as shown in FIG. 1. Note that, FIG. 1 is a plan view schematically showing an arrangement of a pixel on a TFT array substrate 11 of the liquid crystal display device. Further, FIG. 2 shows a cross-sectional view corresponding to line A-A of FIG. 1.

As shown in FIGS. 1 and 2, the TFT array substrate 11 is arranged so that gate lines 13 and source lines 14 are arranged in a matrix manner on a glass substrate (insulation substrate) 12, and TFTs 15 are provided in the vicinity of areas where the gate lines 13 and the source lines 14 cross. Further, a storage capacitance line 16 is provided between each of two adjacent gate lines 13.

As shown in FIG. 2, a gate electrode 17 branching from the gate line 13, and the storage capacitance line 16 are formed on the glass substrate 12. On the gate electrode 17 and the storage capacitance line 16, a gate insulation layer 18 is formed.

On the gate electrode 17, an amorphous silicon layer 19, an n+ type silicon layer 20, a source electrode 21, and a drain electrode line 22 are formed via the gate insulation layer 18, so that the TFT 15 is formed. Here, the source electrode 21 branches from the source line 14.

The drain electrode line 22 extends from the TFT 15 to a contact hole 23. The function of the drain electrode line 22 is to serve as a drain electrode of the TFT 15, electrically connect the TFT 15 with a pixel electrode 24, and form an electric capacitance with the storage capacitance line 16 at the contact hole 23. Further, on the drain electrode line 22, a passivation layer 25 covering the TFT 15; an interlayer insulation layer 26 for planarization, etc.; and the pixel electrode 24 for applying a voltage to liquid crystal, etc., are formed.

Hereinafter a portion on the glass substrate 12 where the pixels as described above are provided is referred to as a pixel formation area 61, and illustrated in FIG. 4 to be described later.

Further, the liquid crystal display device in accordance with the present embodiment includes a terminal section 28 shown in FIG. 31(a). The terminal section 28 is a connection section for connecting the TFT array substrate 11 with an external circuit substrate, a driver IC, and the like. Note that, FIG. 31(a) is a plan view schematically showing an arrangement of one terminal section on the TFT array substrate 11 of the liquid crystal display device. Further, FIG. 31(b) shows a cross-sectional view corresponding to line Q-Q of FIG. 31(a).

As shown in FIG. 31(b), the terminal section 28 is arranged so that a terminal line 30, the gate insulation layer 18, and a terminal electrode 29 are sequentially provided in this order on the glass substrate 12. The terminal electrode 29 is provided to improve the electrical connection with the external circuit substrate and driver IC, for example. The terminal line 30 is connected to the gate line 13, the source line 14, and the like, in the pixel formation area.

Note that, in the present embodiment, both of the terminal line 30 and the terminal electrode 29 are formed on the glass substrate, and composed of silver-indium alloy which is the silver alloy material having the same composition. However, a ratio of indium to silver in the silver alloy material in the terminal line 30 is different from a ratio of indium to silver in the silver alloy material in the terminal electrode 29. Here, the composition ratio is adjusted such that the ratio of indium to silver in the terminal line 30 is smaller than the ratio of indium to silver in the terminal electrode 29.

Hereinafter, portions on the glass substrate 12 where the terminal sections 28 as described above are provided are referred to as terminal section formation areas 62, and illustrated in FIG. 4 to be described below.

FIG. 4 is a plan view of the TFT array substrate 11. The pixel formation area 61 and the terminal section formation areas 62 are arranged on the glass substrate 12 as shown in FIG. 4. The pixel formation area 61 and the terminal section formation areas 62 are provided with many pixels and terminal sections, respectively, as shown in FIGS. 1, 2, and 31.

In the present embodiment, the pattern formation equipment as explained in First Embodiment is used to manufacture the TFT array substrate 11, thus the details of the apparatus is omitted here.

Note that, in the present embodiment, in order to form on the glass substrate 12, the terminal line 30 and the terminal electrode 29 respectively using different silver alloy materials that contain indium in different ratios, as shown in FIG. 31(b), it is necessary that the ink-jet head 33 has a mechanism that can at least discharge fluid wiring materials respectively composed of the silver alloy materials having different composition ratios.

For example, as shown in FIGS. 32(a) and 32(b), the ink-jet head 33 may be provided with a first head 33 a and a second head 33 b in this order along a direction of movement of the ink-jet head 33 (in the arrow direction). The first head 33 a is used for discharging fluid wiring material composed of low-resistance material for the line section, and the second head 33 b is used for discharging fluid wiring material composed of plasma resistance material for the terminal section. Here, the ink-jet head 33 discharges either one of the fluid wiring materials by appropriately selecting between the first head 33 a and the second head 33 b.

The details of the formation of the terminal section using the ink-jet head 33 as arranged above will be described later.

Here, a manufacturing method of the TFT array substrate 11 in the liquid crystal display device of the present embodiment will be explained, but the explanation of the same steps as those explained in First Embodiment will be omitted here.

Namely, in the present embodiment, the TFT array substrate 11 is manufactured in accordance with the manufacturing process shown in FIG. 6 as in First Embodiment.

Therefore steps different from those in First Embodiment will be mainly explained here.

(Gate Line Pre-Processing Step 101)

The gate line pre-processing step 101 is the same as that in First Embodiment, thus their explanation is omitted here.

(Gate Line Formation Step 102)

Next, the following will explain the gate line formation step 102 with reference to FIGS. 7(b), 7(c), 8(b), and 8(c).

FIGS. 7(b), 7(c), 8(b), and 8(c) are drawings showing states when the gate line formation step 102 is completed. FIGS. 7(b) and 8(b) are plan views of the glass substrate 12 at the pixel formation area 61 and the terminal section formation area 62, respectively. FIG. 7(c) is a cross-sectional view corresponding to line C-C of FIG. 7(b). FIG. 8(c) is a cross-sectional view corresponding to line D-D of FIG. 8(b).

Next, fluid wiring material is applied to the hydrophilic areas (lyophilic areas) such as the gate line formation area 41, using the pattern formation equipment. The fluid wiring material may be silver-copper alloy, silver-palladium alloy, silver-gold alloy, etc., coated with organic material, but the fluid material used here is a material prepared by dispersing into an organic solvent, silver-indium alloy particles coated with organic material as shown in Examples 3 through 6. Namely, this material can widely achieve smooth flatness, plasma resistance, and low resistance by the adjustment of the indium content, and can be used after appropriately blended in accordance with usage such as portions requiring low resistance or portions requiring plasma resistance. Silver and indium contained in the fluid wiring material is appropriately adjusted so that an amount of indium with respect to silver is not more than about 10% by weight with respect to silver. The width of the line is set to about 50 μm, and an amount of the wiring material discharged from the ink-jet head 33 is set to 40 pl.

The alloy particles may be produced in the following manner. Namely, appropriate amounts of silver and indium are mixed and alloyed using arc melting and ion beam. Using this alloy as master alloy, the alloy is evaporated again in a rare gas and an organic solvent atmosphere, and particles thus produced are dispersed in the solvent.

Note that, the ratio of indium to silver in the fluid wiring material is set here so that the silver-indium alloy at portions to be exposed to plasma contains indium in a ratio of about 10% of indium by weight with respect to silver, in view of dry etching in the gate insulation film and semiconductor film processing step 104, and passivation film processing step 109 to be performed later.

On the other hand, the gate line is required to have low resistance for the following reasons. The gate line should not enlarge surface roughness due to grain growth, etc., with respect to a temperature of 300° C. applied in the subsequent gate insulation film and semiconductor film formation step 103. Further, change in response characteristics due to signal delay between a TFT near the driver IC and a TFT remote to the driver IC, caused by the resistance of the gate line, should be as low as possible because a signal is applied to the gate line for a short period of few tens μ sec. In view of this, the silver-indium alloy containing indium in a ratio of about 5% by weight with respect to silver is used at portions that are covered with the gate insulation layer and passivation film and are not directly exposed to plasma. However, the ratio can be appropriately selected depending on the manufacturing process, the desired performance of the TFT array substrate, and the like.

On the surface that has been subjected to the hydrophilic (lyophilic) processing, the fluid wiring material discharged from the ink-jet head 33 extends along the gate line formation area 41. Accordingly, application is performed in such a manner that the fluid wiring material is discharged at appropriately adjusted intervals of about 50 μm to 500 μm. After the application, the glass substrate 12 is baked for one hour at 300° C. so that the gate line 13, gate electrode 17, storage capacitance line 16, and terminal line 30 composed of silver and indium are formed.

Here, since the gate line 13 and the like are composed of silver and indium, the gate line 13 and the like have sufficient heat resistance with respect to the 300° C. condition, and do not lose their surface flatness. In contrast, with respect to the same condition, conventional silver significantly loses its surface flatness, and causes a leak between an upper layer and the bottom layer, resulting in poor quality.

Further, the gate line 13 and the like are directly in contact with the glass substrate 12. Since the gate line 13 and the like are composed of silver and indium in the present embodiment, the gate line 13 and the like have sufficient adhesion to the glass substrate, and do not separate from the glass substrate in the later steps. In contrast, since the conventional silver has low adhesion, the conventional silver separates from the glass substrate in the later steps, resulting in poor quality.

Note that, the temperature for the baking is set to 300° C. here because the processing heat of about 300° C. is to be applied in the following gate insulation film and semiconductor film formation step 103. Therefore the temperature for the baking is not limited to this temperature.

Next, the formation of the gate line using an ink-jet method will be described. FIG. 35 shows a schematic diagram of the gate lines as a whole. The gate lines 13 are composed of the storage capacitance lines 16 and the terminal lines 30. The gate lines 13 connect to terminals of the driver IC (not shown) at an end portion of the substrate. Further, the storage capacitance lines 16 are united into the terminal line 30 at one end portion. Note that, in FIG. 35, the same reference numbers are assigned to members corresponding to the members shown in FIGS. 7(a) through 7(c) and 8(a) through 8(c).

As described above, the gate line section is composed of the silver alloy material containing indium in a ratio of 5% by weight with respect to silver, and the terminal lines and the terminals are composed of the silver alloy material containing indium in a ratio of 10% by weight with respect to silver. These different types of wiring materials are separately loaded to the droplet supply device of the ink-jet apparatus shown in FIG. 5, and the ink-jet heads 33 are also provided in the number of types of the fluid wiring materials. Here, two heads (see FIGS. 32(a) and 32(b)) are prepared respectively for the material containing indium in an amount of 5% by weight with respect to silver and the material containing indium in an amount of 10% by weight with respect to silver.

FIGS. 32(a) and 32(b) show this situation. FIG. 32(a) shows a state in which the wiring material containing indium in a ratio of 5% by weight with respect to silver is applied to the gate line formation area 41 shown in FIG. 7(a) using the first head 33 a dedicated for this material. Next, as shown in FIG. 32(b), the wiring material containing indium in a ratio of 10% by weight with respect to silver is applied to the terminal line formation area 44 shown in FIG. 8(a) using the second head 33 b dedicated for this material.

In this case, because the two materials are fluid, the two materials mix with each other on the glass substrate 12 after discharged. Therefore the two materials are electrically connected with each other after the baking step to be performed later. Further, at a portion where the two materials mix with each other, an intermediate state of the two liquids is partly formed. Here, the two wiring materials should be switched over sufficiently before reaching the terminal line formation area 44 in such a manner that the intermediated state of both the materials does not flow into the terminal section in the terminal line formation area 44 shown in FIG. 8(a), for example, so as not to cause the terminal section to have the composition ratio of the intermediate state. For example, the materials may be switched at a distance of about few hundreds μm before reaching the terminal section. Of course the terminal section may be subject to the application first.

Further, the gate electrode 17 shown in FIG. 7(b) may be formed with the silver alloy material containing a large amount of indium. The gate electrode 17 is especially required to have excellent flatness because the semiconductor layer is to be formed on the gate electrode 17 in the later step. Further, the effect of preventing the grain growth can be achieved more stably if the silver alloy material contains indium in a ratio of 10% by weight with respect to silver, than in a case where the silver alloy material contains indium in a ratio of 5% by weight with respect to silver. Further, another material that can achieve similar surface flatness is a material in which high-melting point metal such as cobalt, titanium, niobium, and molybdenum is mixed in silver.

The line formed as described above is further arranged so that at least two portions in the same line have different properties. Here, the line section and the electrode section of the gate line 30 have different properties from each other. Specifically, by varying a ratio of indium with respect to silver in the silver-indium alloy as the wiring material, as described above, it is possible to cause the different sections (portions) to have different properties.

Note that, different wiring materials may be also used to achieve the portions having different properties.

Here, the same line means a line having continuous shape, and a unit of a plurality of lines that form the circuit substrate.

Further, the line is preferably composed of a single layer, as described above. On the other hand, the conventional line has a multi-layer structure for the following reasons.

Conventionally, (A) performance such as invariance of surface property with respect to applied heat, namely heat resistance; resistance to an etching gas in a plasma during the dry etching processing, namely, plasma resistance; and adhesion, and (B) resistance value as the line are both attained at the same time conventionally by overlapping wiring materials in layers. Specifically, the wiring material is arranged to mainly consist of low-resistance metal such as aluminum, for example, and contain a small quantity of silicon or copper for attaining heat resistance. Then, titanium, molybdenum, or the like, is used as adhesion material formed under the wiring material, and tantalum, niobium, or the like, is used as plasma resistance material formed on the wiring material.

As described above, conventionally, two-layer or three-layer structure is used to achieve the target performance. In particular, the wiring material as used in the TFT array substrate is often required to simultaneously attain two or more items of the various types of performance as described here. Accordingly, forming films for one line requires the film formation step in a plurality of times, such as twice or three times, and requires a plurality of apparatuses corresponding to the steps, thereby increasing investment in equipment. Further, in processing the formed films into a pattern, the materials for etching cannot be flexibly selected if the layered films are processed using the same etching material.

Further, a thickness of the formed film in the TFT array substrate may be limited in view of the later steps. This is because a difference in level caused by the layered film may break a film, such as a line, formed thereon. In addition to the limitation on the film thickness, most materials formed on the layer, namely, such plasma resistance material as tantalum and niobium, have large resistivity.

The low-resistance metal portion mainly contributing to electric conduction is demanded to have as low resistance as possible. Therefore it is quite difficult to seek a material having low resistance, or seek an alternative material if the alloy is already made in accordance with other required performance.

Further, the low resistance may be achieved by increasing the width of the line. However, it is difficult to increase the width of the line because a liquid crystal panel, for example, is required to achieve brighter screen by increasing an aperture ratio of pixels.

In view of this, forming the line in a single layer as in the present invention is quite important in terms of both cost and performance, in order to solve the foregoing problems. This applies to not only the case where fluid material is used, but also to a case where sputtering or evaporation is used.

For using fluid material, however, an ink-jet method, which can realize the separate application, can be applied so meaning of the film formation in a single layer becomes bigger. Note that, forming the fluid material in layers using the ink-jet method is still a problem in terms of manufacturing cost such as investment in equipment and tact time.

Another advantage of the fluid material is that materials in the same system can be used in a case where the mixing ratio of indium in the silver-indium system is adjusted as in the present embodiment, in particular. The materials in the same system are materials in which a solvent in which particle material is dispersed, or protective colloid which disperses particles and prevents coagulation, has similar property; and materials that do not generate unwanted precipitation when the solvents are mixed together if the metal is contained as complex condition in the solvents. In a case where particles are used, solvents in the same system suffer from little shock when mixed together, therefor particles are not much coagulated or precipitated due to the mixing. If fluid materials respectively composed of solvents having remarkably different polarities from one another are mixed together, the fluid materials easily cause separation or coagulation. Further, in terms of the ink-jet head that discharges fluid materials in the same system, it is possible to have a wide selectivity of material for constituting the head with respect to the fluid wiring material, namely, adhesive agent used in the head, for example, thereby facilitating the tuning of the head with respect to the fluid wiring material. Of course, solvents in different systems can be mixed together if the solvents are discreetly selected to prevent coagulation and precipitation. However, such selection and tuning require a huge time in most cases. In view of this, the materials in the same system are quite useful.

Note that, the single layer here refers to a line formed in one layer, in terms of the formed film; and a functional film that can achieve the performance required for the line, which is formed by the application at a time, in terms of fluid material. For example, the notion of the single layer does not exclude the following cases, for example. Namely, as in the hydrophilic and hydrophobic (lyophilic and lyophobic) processing, a layer that is only required for the separate application and does not actively improve the adhesion is provided and then formed in the later steps; a film that imparts adhesion and improves the adhesion is first formed, and then the film arranged as explained above is applied at a time.

(Gate Insulation Film and Semiconductor Film Formation Step 103)

In the present embodiment, the gate insulation film and semiconductor film formation step 103 is the same as that in First Embodiment, thus their explanation is omitted here.

(Gate Insulation Film and Semiconductor Film Processing Step 104)

Next, the following will explain the gate insulation film and semiconductor film processing step 104 with reference to FIGS. 12(a), 12(b), 13(a), and 13(b).

FIGS. 12(a), 12(b), 13(a), and 13(b) are drawings showing states when the gate insulation film and semiconductor film processing step 104 is completed. FIGS. 12(a) and 13(a) are plan views of the glass substrate 12 at the pixel formation area 61 and the terminal section formation area 62, respectively. FIG. 12(b) is a cross-sectional view corresponding to line G-G of FIG. 12(a). FIG. 13(b) is a cross-sectional view corresponding to line H-H of FIG. 13(a).

In the gate insulation film and semiconductor film processing step 104, photolithography is used for the processing.

First, the amorphous silicon film 46 and the n+ type silicon film 47 are processed by first photolithography in such a manner that the amorphous silicon film 46 and the n+ type silicon film 47 remains in an island-like manner above the gate electrode 17 in the pixel formation area 61, and do not remain in the terminal section formation area 62. Consequently, the amorphous silicon layer 19, and an n+ type silicon processing film 48 to be the n+ type silicon layer 20 are obtained. Then, etching using a dry etching method is performed while introducing mixed gas of sulfur hexafluoride (SF₆) gas and hydrogen chloride (HCl) gas. Since the gate insulation film 45 covers the entire surface of the substrate until this point, the terminal line 30 and the like are not exposed to the dry etching atmosphere.

Subsequently, the gate insulating film 45 is processed by second photolithography. In the terminal section formation area 62, the gate insulation film 45 is partly etched so that the gate insulation layer 18 and an opening section 49 are obtained. The etching is performed using a dry etching method while introducing mixed gas of CF₄ gas and O₂ gas.

In the dry etching of the gate insulation film 45, the terminal line 30 is exposed to the dry etching atmosphere at the opening section 49 and other electrical connection portions (not shown) formed in the terminal section formation area 62. This is because a dry etching method, though well controllable, cannot be completely free from over etching in actual manufacturing.

Here, if the terminal line 30 is composed of silver as in a conventional technique, the terminal line 30 does not have plasma resistance. Accordingly, the terminal line 30 is significantly etched at the opening section 49, resulting in poor quality. In contrast, in the present embodiment, the terminal line 30 is composed of silver and indium, and a ratio of indium with respect to silver is set to about 10% by weight. Therefore the terminal line 30 has plasma resistance and can withstand the dry etching as described above.

(Source and Drain Lines Pre-Processing Step 105)

The source and drain lines pre-processing step 105 is the same as that in First Embodiment, thus their explanation is omitted here.

(Source and Drain Lines Formation Step 106)

The source and drain lines formation step 106 is the same as that in First Embodiment, thus their explanation is omitted here.

Note that, the lines having the single-layer structure similarly have advantages as explained in the gate line formation step.

(Channel Section Processing Step 107)

The channel section processing step 107 is the same as that in First Embodiment, thus their explanation is omitted here.

(Passivation Film and Interlayer Insulation Layer Formation Step 108)

The passivation film and interlayer insulation layer formation step 108 is the same as that in First Embodiment, thus their explanation is omitted here.

(Passivation Film Processing Step 109)

The passivation film processing step 109 is the same as that in First Embodiment, thus their explanation is omitted here.

(Pixel Electrode Formation Step 110)

In this final step, an ITO (indium tin oxide) film to be the pixel electrode 24 and terminal electrode 29 are formed by a sputtering method. Here the substrate temperature is set to 200° C. Then, the ITO film is patterned using photolithography, so that the TFT array substrate 11 as shown in FIGS. 1, 2, 31(a), 31(b), and 4 is obtained.

As described above, the material of the present invention has excellent adhesion to a glass substrate, which cannot be achieved by the conventional material made of only silver. Therefore the material of the present invention can withstand the series of manufacturing process without causing a defect due to the separation of the gate line or the like from the substrate.

Further, the material of the present invention has excellent heat resistance that cannot be achieved by the conventional material made of only silver. With this, it is possible to obtain the gate line 13, storage capacitance line 16, gate electrode 17, and the like, having good surface property such that the surfaces of the lines do not become rough even if the substrate is exposed under the 300° C. high temperature condition as in the present example. Accordingly, an electric leak between the gate line 13, storage capacitance line 16, gate electrode 17, or the like, and the source line 14, semiconductor layer 27, source electrode 21, or the like, to be formed thereon via the gate insulation layer 18 is prevented. This improves the yield of TFT array substrates and stabilizes the characteristics of the TFTs.

Above all, the high plasma resistance provided to the material of the present invention enables the manufacturing process as described above.

In the present embodiment, dry etching is carried out in a total of three steps, namely, the etching of the gate insulation layer 18 in the gate insulation film and semiconductor film processing step 104, etching of the n+ silicon processing film 48 in the channel section processing step 107, and etching of the silicon nitride film 55 in the passivation film processing step 109. Here, if the lines, electrodes, and the like, are formed using only silver as in the conventional technique, the lines, electrodes, and the like, are etched due to over etching or etched when used as etching masks for other films, thus resulting in poor quality. In contrast, the wiring material of the present invention, as in the present embodiment, has excellent plasma resistance, thereby causing no defect.

As described above, dry etching is used many times in manufacturing the TFT array substrate. Accordingly, high dry etching resistance (plasma resistance) is required for the material that composes the lines, electrodes, and the like. The material mainly consisting of silver and containing silver as in the present invention has high plasma resistance, and extremely excels as a material for composing the lines, electrodes, and the like, on the TFT array substrate, in particular.

Further, the material of the present invention is especially effective in a case as in the present embodiment where the source line 14, semiconductor layer 27, source electrode 21, and the like, are plotted and formed using pattern formation equipment employing a system such as an ink-jet method. In such a case, the source line 14 and the like are used as etching masks for forming the n+ silicon film 20, and are exposed to the dry etching atmosphere throughout the etching. Therefore it is difficult to apply this process to the conventional source line 14 and the like composed of only silver. In contrast, use of the material of the present invention enables the manufacturing of a TFT array substrate using such pattern formation equipment.

As described above, the silver alloy material of the present invention is particularly suitable for the manufacturing process using the application apparatus such as an ink-jet apparatus, and beneficially used when contained in fluid wiring material. Note that, the silver alloy material of the present invention is also beneficially used in a manufacturing method that does not use the pattern formation equipment, as described later.

The present embodiment employs a six-mask process in which an exposing process using a photomask and a developing process are performed in a total of six times. A five-mask process is also widely used to manufacture TFT array substrates at lower cost. In this case, the method is to form the gate insulation layer 18 and the passivation layer 25 by consecutively etching the gate insulation film 45 and the silicon nitride film 55. However, in this case, the revealed portion of the drain electrode line 22, in particular, is exposed to the dry etching atmosphere for a long time, and has to withstand the harsh process condition.

In this respect, the substrate during the etching will be examined. First, during the etching of the silicon nitride film 55, no problem occurs because the entire surface of the line is covered with the film. However, during the etching of the gate insulation film 45, the revealed portion of the drain electrode line that is generated at the contact hole 23 is directly exposed to the dry etching atmosphere constantly throughout the etching. This is a very long and harsh process condition, compared with the over etching alone in the six-mask process.

Therefore, in the five-mask process as described above, high plasma resistance is especially required for the drain electrode line 22. The silver alloy material of the present invention, typified by the silver alloy material containing silver and indium, has high plasma resistance. Therefore the silver alloy material of the present invention can be used in the five-mask process, and has a broad usable range.

Note that, the present embodiment uses the six-mask process and forms the terminal line 30 and the gate line 13, etc., at the same time, but the scope of the present invention is not limited to this. In most of the current manufacturing methods in which a silicon nitride film to be the gate insulation layer or passivation layer 25 are entirely formed on a substrate and then partly removed, a portion of the film should be removed for electrical connection. Accordingly, the electrodes, lines, or the like, provided under the removed portion of the silicon nitride film inevitably require plasma resistance with respect to over etching. The present invention provides a material having excellent plasma resistance, and has an excellent effect on the manufacturing process of these TFT array substrates.

In the present embodiment, the fluid wiring material used is a material prepared by dispersing into an organic solvent, silver-indium alloy particles coated with organic material. The fluid wiring material here is set to contain indium in a ratio of about 10% by weight with respect to silver. However, the ratio can be appropriately selected depending on the manufacturing process, the desired performance of the TFT array substrate, and the like.

Further, the form of the fluid wiring material is not limited to the form that contains silver and indium as silver-indium alloy particles. The form may be such that silver particles and indium particles are separately produced, and then dispersed in a solvent independently from each other. Further, the form of silver and indium is not limited to the particles, and may be silver or indium metal compound contained in the solvent.

In the present embodiment, the silver alloy material containing silver and indium is used to form the lines, electrodes, and the like, such as the source line 14, gate line 13, and the like, but the material is not limited to this. The silver alloy material containing silver and zinc may be used instead. Further, the gate line 13 and the like may be formed using the silver alloy material that is arranged to contain silver and at least one element selected from the group consisting of tin, zinc, lead, bismuth, indium, and gallium. Further, the silver alloy material may be arranged to mainly consist of not only silver but also aluminum or copper. Further, in addition to these elements, the silver alloy material may be arranged to contain at least an element selected from the group consisting of aluminum, copper, nickel, gold, platinum, palladium, cobalt, rhodium, iridium, ruthenium, osmium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, and neodymium.

The following will explain the details of the line formation in the gate line formation step 102 and in the source and drain lines formation step 106.

First, the gate line formation step 102 will be explained with reference to FIGS. 32(a) through 32(e).

First, as shown in FIG. 32(a), the first head 33 a of the ink-jet head 33 is used to discharge the fluid wiring material composed of the low-resistance material for the line section so as to form the terminal line 30 at a line formation area on the glass substrate 12. The glass substrate 12 has been subject to the hydrophilic and hydrophobic processing (lyophilic and lyophobic processing) in the gate line pre-processing step 101.

Next, as shown in FIG. 32(b), the second head 33 b of the ink-jet head 33 is used to discharge the fluid wiring material composed of the plasma-resistance material for the terminal section so as to form the terminal electrode 29 at a terminal electrode formation area on the glass substrate 12 on which the terminal line 30 has been formed.

Then, as shown in FIG. 32(c), the terminal line 30 and the terminal electrode 29 formed on the glass substrate 12 are baked, and the gate insulation film 45 to be the passivation layer is formed so as to cover the terminal line 30 and the terminal electrode 29.

Subsequently, as shown in FIG. 32(d), a resist material 100 is provided as a mask in such a manner that a portion of the gate insulation film 45 that corresponds to the terminal electrode 29 is open, and a pattern is formed by mask exposure or the like.

Lastly, as shown in FIG. 32(e), the portion of the gate insulation film 45 that corresponds to the terminal electrode 29 is etched, and then the resist material 100 is removed. With this, the terminal section 28 is formed.

If the ink-jet head 33 is provided with two heads respectively having different functions so as to deal with two types of fluid wiring materials, as described above, it is necessary that the ink supply system 36, the control unit 37, and the discharging position information, etc., can also correspond to the two heads.

The terminal section 28 formed as described above is as shown in FIGS. 31(a) and 31(b). Note that, the terminal line 30 contacts and electrically connects the terminal electrode 29.

Since the terminal line 30 is covered with the gate insulation layer 18, the terminal line 30 only needs to have heat resistance and adhesion to a glass substrate among the process resistance. The terminal line 30 does not require plasma resistance because the terminal line 30 is not exposed to a dry etching atmosphere.

For example, if the manufactured circuit substrate is to be used for a large-sized liquid crystal display device, in particular, it is preferable that the electric resistance of the terminal line 30 is as low as possible, because the length of the lines is long in the large-sized liquid crystal display device. In such a case, the terminal line 30 can be arranged to contain 3% of indium by weight with respect to silver and have an electric resistivity of about 4 μΩcm. Further, for the same reason as to the length of the lines, the gate line 13, the gate electrode 17, and the storage capacitance line 16 in the pixel formation area 61 can be also arranged to contain 3% of indium by weight with respect to silver so as to have lower electric resistance.

In contrast, the terminal electrode 29 is exposed to a dry etching atmosphere due to over etching in the etching step for electrical connection. Accordingly, the terminal electrode 29 can be arranged to contain 10% of indium by weight with respect to silver, in view of emphasis on plasma resistance. Since the terminal electrode 29 is much shorter than the gate line 13, source line 14, and terminal line 30 on the TFT array substrate, the terminal electrode 29 can have a larger electric resistivity than the other lines.

Of course, both of the terminal line 30 and the terminal electrode 29 may be arranged in the same manner as in First Embodiment, namely, may be arranged to contain 10% of indium by weight with respect to silver. However, by performing the separate application in response to each performance required for each of the parts, it is possible to form the lines, electrodes, and the like, having lower electric resistance as a whole, thereby realizing a circuit substrate having a larger size, a display device having a larger size, and the like.

Here, the ink-jet head 33 uses the first head 33 a and the second head 33 b to discharge two types of fluid wiring materials respectively containing different amounts of indium with respect to silver, thereby forming the terminal line and terminal electrode. Specifically, a fluid wiring material that contains indium in an amount of 3% by weight with respect to silver when formed into the terminal line 30 is discharged to a portion to be the terminal line 30.

On the other hand, a fluid wiring material that contains indium in an amount of 10% by weight with respect to silver when formed into the terminal electrode 29 is discharged to a portion to be the terminal line connection section 30. The fluid wiring material the same as that of the terminal line 30 is discharged to portions where the gate line 13, the gate electrode 17, and the storage capacitance line 16 are to be formed in the pixel formation area 61. After discharged, the fluid wiring materials are baked for one hour at 300° C. as in First Embodiment. With this, the predetermined terminal line 30, terminal electrode 29, and the like, are obtained.

In the present embodiment, it is important that (A) the pattern formation equipment employing a system such as an ink-jet method can carry out separate application to the surface of the substrate, (B) different parts of the lines and the like formed in the same step respectively require different plasma resistance or conductivity, and (C) the relationship between the indium content, conductivity, and process resistance of the material of the present invention is combined well. With this, it is possible to manufacture a large-sized TFT array substrate that can be easily manufactured and that has good electric properties.

Note that, in the present embodiment, the terminal line 30 and the terminal electrode 29 are separated by a boundary that separates the materials having different contents of indium, but the present invention is not limited to this. The indium content in the materials may gradually change in the vicinity of the boundary. This gradual boundary may be formed in such a manner that the fluid wiring materials mix with each other by themselves, or intentionally mixed with each other by alternate discharging of the two types of fluid wiring materials.

Of course, an important point of the present embodiment is to provide the lines, electrodes, and the like, containing an increased amount of indium at portions which are required in the TFT array substrate 11 and which are exposed to a dry etching atmosphere in the manufacturing process.

As described above, even if the silver alloy material of the present invention contains a comparatively low amount of indium, namely, 1% by weight or 3% by weight, for example, with respect to silver, the silver alloy material can be applied to many manufacturing processes if the separate application is performed. Therefore the silver alloy material can be appropriately used as a material having especially low electric resistance for composing the lines and electrodes such as the gate line 13.

Note that, in the present embodiment, the silver alloy material containing silver and indium is used to form the gate line 13 and the like, but the material is not limited to this. The silver alloy material containing silver and zinc may be used instead. The gate line 13 and the like may be formed using the silver alloy material that is arranged to contain silver and at least one element selected from the group consisting of tin, zinc, lead, bismuth, indium, and gallium. Further, the silver alloy material may be arranged to mainly consist of not only silver but also aluminum or copper. Further, in addition to these elements, the silver alloy material may be arranged to contain at least an element selected from the group consisting of aluminum, copper, nickel, gold, platinum, palladium, cobalt, rhodium, iridium, ruthenium, osmium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, and neodymium.

Further, the silver alloy material having different compositions, such as silver alloy material containing indium, silver alloy material containing zinc, etc., may be respectively used at different portions on the TFT array substrate 11.

Next, the following will explain the details of the source and drain lines formation step 106. Here, the wiring materials are arranged such that an amount of indium with respect to silver is 3% by weight in the source electrode 21 and source line 14, and 10% by weight in the drain electrode line 22.

Further, within the drain electrode line 22, wiring material containing 3% of indium by weight with respect to silver and wiring material containing 10% of indium by weight with respect to silver may be separately applied in such a manner that plasma resistance increases in the vicinity of the contact hole 23. Similarly, such separate application may be performed at any portion on the TFT array substrate of the present embodiment.

Note that, the wiring material used in the present embodiment is not limited to the material composed of silver and indium, and may be silver alloy material containing silver and zinc. Further, the source line 14 and the like may be formed using the silver alloy material that is arranged to contain silver and at least one element selected from the group consisting of tin, zinc, lead, bismuth, indium, and gallium. Further, in addition to these elements, the silver alloy material may be arranged to contain at least an element selected from the group consisting of aluminum, copper, nickel, gold, platinum, palladium, cobalt, rhodium, iridium, ruthenium, osmium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, and neodymium.

Further, the silver alloy material having different compositions, such as silver alloy material containing indium, silver alloy material containing zinc, etc., may be respectively used at different portions on the TFT array substrate.

Note that, in manufacturing the TFT array substrate 11, the separate application may be performed in both of or one of the gate line formation step 102 and the source and drain lines formation step 106.

Here, the following will explain a portion at which different materials contact with each other in a case where the different wiring materials are separately applied to the wiring section, the terminal section, etc., in accordance with usage.

As shown in FIG. 33(a), for example, a material M is applied as the terminal line 30 which is the line section. Then, as shown in FIG. 33(b), a material N is applied to a portion corresponding to the terminal electrode 29 that forms the terminal section. Here, the material M and the material N contact with each other or mix with each other at a boundary portion P.

FIGS. 34(a) through 34(c) show states that are expected to occur at the boundary where the different materials M and N contact with each other after the application using the ink-jet method.

FIG. 34(a) shows a case where the materials M and N in liquid form mix with each other at the boundary so as to form a state different from the materials M and N, namely, an intermediate state (intermediate area).

An extent of the materials that mix with each other to form the intermediate state depends on the mixing ratio of the material M and N, but also relates to how long the contained solvent stays after applied. Namely, if the solvent is dried, the mixing of the materials due to the fluidity of the liquid no longer occurs. Even though the intermediate state of the materials M and N is generated by the fusion of the metal particles during the baking, the extent of the intermediate state here is considered to be very narrow compared with the intermediate state generated by the mixing of the materials in liquid form. Here, the mixing of the materials in liquid form is noted, and the boundary between the materials M and N is quite unclear in this case.

FIG. 34(b) shows a state where the solvent of the material M that applied first is substantially dried and then the material N is applied, so that the materials M and N do not mix with each other.

In this state, since the materials M and N do not mix with each other, the boundary between the materials M and N exists comparatively clearly. Note that, the intermediate state is generated by the fusion of particles contained in the materials M and N during the baking.

FIG. 34(c) is a medium case of the states shown in FIGS. 34(a) and 34(b), and shows a state where the material M changes to a liquid state again by the solvent of the material N applied later, so that the boundary between the material M and N becomes unclear. In this case, a portion where the materials mix with each other is narrower compared with the case shown in FIG. 34(a). Thus, a virtual boundary can be drawn at the middle of the mixed portion.

It is important in the present embodiment that the materials M and N are electrically connected with each other after baked. The materials M and N are electrically connected with each other in all of the states shown in FIGS. 34(a) to 34(c), and the present invention can employ any of the states. However, as described later, for forming a resistance by actively using the intermediate state generated by the mixture of the materials M and N, the state shown in FIG. 34(a) is preferable, and end portions of the resistance are preferably in the state shown in FIG. 34(b) or 34(c). Note that, the explanation here focuses only on the boundary between the materials M and N. The smooth flatness of the surface during the application is not related to the present explanation, thus the diagrams show the states by means of the planarized surfaces.

By using the present invention, it is possible to form the resistance and adjust the resistance of the line by appropriately combining the wiring material having low resistance and the wiring material alloyed to have high resistance. An example will be explained as below.

In a schematic diagram of gate lines in FIG. 35, the terminal lines that connect the terminal electrodes of the driver IC with the gate lines are arranged as follows, so that the terminal lines have a uniform length. Namely, a short distance portion of terminal line that connects a center portion of the driver IC with gate lines is arranged to have a zigzag shape. On the other hand, a long distance portion of terminal line that connects an edge portion of the driver IC with gate lines is arranged to have a linear shape.

Here, a zigzag pattern, as shown in FIG. 36(a), whose length is D and length of one folded part of the line is L is assumed. In FIG. 36(a), the line is folded four times, and the total length of the line is about 8L. Therefore the resistance is about 8L/D times, compared with a case where the distance D is linearly connected.

For example, if D=600 μm and L=150 μm, then 8L/D=2. Here, the resistivity of the line should be doubled, provided that the width and film thickness of the line is unchanged.

The resistance of the line may be adjusted using three methods as below.

(1) A material having a desired resistivity is used to form the line.

(2) Materials having different resistivities are blended to form the line.

(3) The shape and film thickness of the line is changed.

In the method (1), a material M that contains metal portion having low resistivity and a material N that contains metal portion having high resistivity are prepared. Then, the material M is used to form the line and the material N is used at a portion to form the resistance, as shown in FIGS. 33(a) and 33(b), so that the resistance is formed. A resistivity is about 6.1 μΩcm (Example 5) when alloy contains indium in a ratio of 5% by weight with respect to silver, and 12.3 μΩ·cm (Example 6) when alloy contains indium in a ration of 10% by weight with respect to silver. Accordingly, if this method is applied to the case where D=600 μm and L=150 μm as shown in FIG. 36(a), it is possible to form the resistance using a linear line without using a zigzag pattern, as shown in FIG. 36(b), in a case where the material M is the alloy containing indium in a ratio of 5% by weight with respect to silver and the material N is the alloy containing indium in a ratio of 10% by weight with respect to silver, provided that the film thickness and width of the line is unchanged.

In the method (2) where the intermediate resistance value is adjusted by use of the materials M and N, the preceding first head 33 a in the ink-jet head 33 intermittently discharges the material M, and then the next second head 33 b discharges the material N to gaps between the discharged material M, as shown in FIGS. 37(a) and 37(b), for example. With this, it is possible to mix the materials M and N to obtain a line (intermediate) having a resistance value formed by the materials M and N.

Here, the mixing ratio of the materials M and N can be adjusted by varying intervals and ratio for discharging the materials M and N.

The following will explain another example where the intermediate as described above is formed.

A ratio of the material M to be discharged in an example shown in FIGS. 38(a) and 38(b) is different from that in an example shown in FIGS. 39(a) and 39(b). FIGS. 38(a) and 38(b) show the example where the material M is discharged one out of three drops. FIGS. 39(a) and 39(b) show the example where the material N is discharged two out of three drops. If the lines are arranged as shown in FIG. 34(b), and have the same film thickness, line width, amount of the discharged droplet, and discharging intervals, the line shown in FIGS. 38(a) and 38(b) has a higher resistance value than that in FIGS. 39(a) and 39(b). As described above, the resistance value can be adjusted in accordance with the ratio of the discharging number of the material M to that of the material N. Of course, the resistance value may be appropriately adjusted by changing the film thickness, the line width, the discharging amount, and the discharging intervals.

Further, if the cross-section of the line is in the state as shown in FIG. 34(a), the resistance value is not necessarily an intermediate resistance value in proportion to the mixing ratio. A metal alloy in which different materials are mixed with each other often has a higher resistance value than the intermediate resistance value of both the materials. Further, if the metals are mixed in a ratio that forms a compound, the resistance may become lower than the intermediate resistance value of the mixed metals. This is because the scattering probability of the conduction electrons that contribute to electric conduction becomes higher when different types of materials are simply mixed, and becomes lower when the different types of materials form the compound which has a defined crystal structure. A phenomenon as in the metal alloy supposedly occurs in the present example because the particles are fused when baked after mixed. If the resistance value is not the intermediate value as described above, the characteristics of the resistance should be examined beforehand.

On the other hand, in a case where the discharged droplets are dried and then overlapped with another droplets, namely, in a case as shown in FIGS. 34(b) and 34(c), the materials M and N contact with each other and do not mix with each other. Here, the resistance value is close to the mean value of the resistance values of the materials M and N. Therefore it is possible to obtain the intermediate resistance value of the materials M and N by adjusting the ratio of discharging amounts of the materials M and N. As described above, it is also possible to adjust the resistance value in a state after the application.

In the case shown in FIG. 34(a), in contrast, the boundary between the materials M and N is not clear. Accordingly, the length of the line as the size of the resistance does not become clear and the resistance value varies. Therefore ends of the resistance are preferably dried as shown in FIG. 34(b), so that the boundary is clearly formed.

FIGS. 38(b) and 39(b) show cross-sectional views of FIGS. 38(a) and 39(a), respectively. In order to clearly distinguish the length of the resistive body, the materials M and N are discharged between the sufficiently dried materials in the end portions, so that the boundary becomes clear as in FIG. 34(b). The materials M and N are mixed in liquid form at the resistance portions, so that the boundary becomes unclear as shown in FIG. 34(a).

The following will explain the method (3) where the width and film thickness of the line is changed, with reference to FIGS. 40(a) through 40(c).

FIG. 40(a) shows a case where the discharging interval is shorter. In this case, the film thickness increases if the concentration and line width of the applied material is unchanged.

On the other hand, FIG. 40(b) shows a case where the discharging interval is longer. Ovals indicated by broken lines are portions on which the droplets are laid down. This diagram shows a case where the material N laid down on two portions in an area at which the resistance is to be formed extends along a hydrophilic (lyophilic) pattern. The area has been made into a hydrophilic (lyophilic) area beforehand by the hydrophilic and hydrophobic (lyophilic and lyophobic) processing. Here, the film thickness is reduced compared with the case shown in FIG. 40(a) where the discharging interval is shorter. As described above, by widening the discharging interval to reduce the film thickness, it is possible to form the resistance having higher value.

As described above, it is possible to produce the materials having various resistance values by appropriately combining the methods (1) to (3).

These methods are effective in a case where a monolithic IC is formed on glass. In an IC process for processing a Si wafer, a resistance is appropriately produced by ion implantation. In a panel made of a large-sized substrate such as a panel of a liquid crystal display device as in the present example, the method employing the ion implantation is not realistic in terms of the apparatus and the price of the apparatus because the scale of the apparatus becomes too large. Therefore the foregoing method is quite effective in forming a circuit substrate that requires a resistance on the substrate.

Further, a material used for the resistance may be silver alloy material containing indium in a varied ratio with respect to silver. As a material having higher resistance, a material such as cobalt and nickel having a high resistivity, or a material such as titanium, niobium, tungsten, and molybdenum having a high melting point may be used either as alloy material mixed with silver or as single material.

Further, as shown in FIG. 40(c), the width of the line may be reduced when a portion at which the line is formed is made into a hydrophilic (lyophilic) area using the hydrophilic and hydrophobic (lyophilic and lyophobic) processing. In this case, the resistance increases if the film thickness is unchanged. As described above, it is possible to control the resistance in accordance with the width of the line.

In FIGS. 38(a), 39(a), and 40(a), the shape of the droplets directly after laid down is clearly drawn in the resistive body portion so as to allow the explanation to be easily understood, but the present invention is not limited to these diagrams. If a droplet is laid down on an area that has been subject to the hydrophilic and hydrophobic (lyophilic and lyophobic) processing, the shape of the droplet directly after laid down may not be retained as shown in the drawings, because the shape of the droplet after laid down extends along the hydrophilic (lyophilic) area. If the droplet remains to be in fluid condition after laid down, the materials M and N may completely mix together as shown in FIGS. 38(b) and 39(b).

Note that, in the present embodiment, the pattern formation equipment employing a system such as an ink-jet method which discharges droplets of fluid wiring material is used. However, the silver alloy material of the present invention also can be beneficially used in a case where such pattern formation equipment is not used. In this case, the TFT array substrate is manufactured in such a manner that the most common conventional method that uses a sputtering or an evaporation method and photolithography is performed in steps corresponding to the steps that use the pattern formation equipment. In this case, instead of the fluid wiring material, a sputtering target, an evaporation source for the evaporation, or the like, is used to obtain the lines, electrodes, and the like, that are formed with the silver alloy composition of the present invention. The silver alloy material of the present invention in this case can be equivalently used beneficially as a material having excellent process resistance such as heat resistance, adhesion, and plasma resistance, as well as low electric resistance.

Note that, the silver alloy material of the present invention can be also used beneficially as a layer in a multilayer wiring structure in which materials are layered in two or more layers. For example, after baked at 300° C., the layer made of the silver alloy material of the present invention does not lose its surface flatness, unlike the material composed of only silver. Further, if the silver alloy material contains indium in a comparatively large amount, namely, 10% by weight, for example, with respect to silver, the silver alloy material has sufficient plasma resistance, and can be effectively used as a protection metal layer for protecting the lines of a layer under the protection metal layer. Further, the layer made of the silver alloy material of the present invention may be used in First Embodiment as all of or part of the source electrode 21 and drain electrode line 22 which directly contact the semiconductor layer 27 for electrical connection. Here, the layer has equivalently excellent heat resistance and adhesion, and is beneficially used in the manufacturing process of the TFT array substrate.

Further, the silver alloy material of the present invention may be used for a light reflective electrode on a TFT array substrate in a reflection type TFT liquid crystal display device, etc. In this case, due to the excellent heat resistance of the silver alloy material of the present invention, the light reflective electrode does not lose its surface flatness after baked at 300° C., for example, unlike the material composed of only silver. Therefore the light reflective electrode can maintain sufficient light reflectance without causing undesigned light scattering. With this, it is possible to fully exhibit the characteristics of the TFT array substrate.

Further, the silver alloy material of the present invention may be also used for a bus electrode and a data electrode on a glass substrate that constitutes a PDP (plasma display panel). These electrodes are provided on a front side glass substrate or back side glass substrate so as to drive the PDP. These electrodes are conventionally arranged to have layer(s) of silver, chromium/copper/chromium, or aluminum/chromium. In order to improve the adhesion of the copper or aluminum layer to the substrate and reduce the mismatch in expansion coefficient, a chromium layer needs to be sandwiched between the glass substrate and the copper or aluminum layer. On the other hand, silver which is conventionally used has a problem in heat resistance, and when baked at high temperature, the crystal grains of silver grow. Therefore silver is difficult to be used as the material for the bus and data electrodes.

In contrast, the silver alloy material of the present invention has excellent heat resistance and adhesion to a glass substrate. Therefore the silver alloy material of the present invention can replace the conventional material such as silver, and can be beneficially used as the bus electrode and the data electrode.

The silver alloy material, the arrangement of the lines, and the method for forming the lines of the present invention may be applied to a display device employing EL (electroluminescence). Unlike a liquid crystal display device, the EL display device may control the gradation of luminance in accordance with an amount of current. In such a case, a current supply line that supplies a current to a luminescent element that composes a pixel is required to be made of a material having low resistance. This is because electrical power consumed by the resistance of the line may cause the reduction of luminous efficiency, heating of the display device, and spots on the display screen.

Further, a circuit substrate that drives an EL element is usually formed using a TFT array, and may be manufactured in a manner similar to that shown in the present example. Therefore the content described in the present example can be applied to a display device employing EL. In particular, a line to be the current supply line and a current supply line from an external circuit to a driver IC may be formed with silver alloy material containing indium in an amount of 3% by weight with respect to silver, and a signal line and a terminal electrode may be formed with silver alloy material containing indium in an amount of 10% by weight with respect to silver.

Further, the silver alloy material, the arrangement of the lines, and the method for forming the lines of the present invention may be also used as wiring material for a flexible substrate and a glass epoxy substrate. On these substrates, connecting terminals may be arranged to contain an increased amount of indium with respect to silver in view of emphasis on oxidation resistance, and the internal line section may be arranged to contain a smaller amount of indium with respect to silver and used as a line having low resistance.

Further, if the silver alloy material of the present invention contains indium in a ratio of not more than 0.5% by weight with respect to silver, in particular, the silver alloy material has an electric resistivity of not more than 2.7 μΩcm, and can beneficially form the lines having low electric resistance that cannot be achieved by conventional aluminum lines. However, because of the low indium content, this silver alloy material does not have sufficient plasma resistance, and generally requires another metal film to be layered thereon. Further, because of the low indium content, the silver alloy material does not have sufficient adhesion to the substrate, and may require pre-processing and the like. Therefore the silver alloy material containing indium in an amount of not more than 0.5% by weight with respect to silver can be also used as a main line of the lines on the circuit substrate if pre-processing is applied.

The following will explain a method for manufacturing a circuit substrate where the wiring material is the silver alloy material containing indium in an amount of not more than 0.5% by weight with respect to silver.

In Second Embodiment, wiring materials respectively having different compositions are separately applied onto the TFT array substrate 71 in the gate line formation step 102 shown in FIG. 6, using the pattern formation equipment typified by ink-jet pattern formation equipment. On the other hand, in Third Embodiment, the separate application of the wiring materials having different compositions is performed in the source and drain lines formation step 106.

In the present embodiment, the lines and the like are formed using a sputtering method in the gate line formation step 102, and these lines are arranged so that the silver alloy material of the present invention and titanium are layered.

FIGS. 41(a), 41(b), 42(a), and 42(b) are drawings showing states when the gate line formation step 102 is completed. FIGS. 41(a) and 42(a) are plan views of the glass substrate 12 at the pixel formation area 61 and the terminal section formation area 62, respectively. FIG. 41(b) is a cross-sectional view corresponding to line R-R of FIG. 41(a). FIG. 42(b) is a cross-sectional view corresponding to line S-S of FIG. 42(a).

In FIGS. 41(a), 41(b), 42(a), and 42(b), a gate line 80, a gate electrode 81, a storage capacitance line 82, and a terminal line 83 have the same multilayer structure composed of two layers. Layers 80 a, 81 a, 82 a, and 83 a on the side close to the glass substrate 12 are composed of the silver alloy of the present invention that contains indium in an amount of 0.2% by weight with respect to silver. Layers 80 b, 81 b, 82 b, and 83 b on the upper side are composed of titanium. The thickness of each of the layers 80 a, 81 a, 82 a, 83 a, 80 b, 81 b, 82 b, and 83 b is set to 0.2 μm.

In the present embodiment, the layers 80 a, 81 a, 82 a, and 83 a that are close to the glass substrate 12 are composed of alloy made of silver and indium, and thus have heat resistance. With this, the gate line 80 and the like are not adversely affected by the baking at about 300° C. in the steps to be performed later. If the gate line 80 and the like are composed of only silver as in the conventional technique, the surfaces of the gate line 80 and the like become remarkably rough with respect to the same condition because the gate line 80 and the like lack heat resistance, and a leak between upper and lower layers occurs.

Further, if the silver alloy material of the present invention contains indium in a ratio of not more than 0.5% by weight with respect to silver, the silver alloy material has an electric resistivity of not more than 2.7 μΩcm as described above, and can beneficially form the lines having low electric resistance that cannot be achieved by conventional aluminum lines. In the present example, the electric resistivity is very low, namely, 2.3 μΩcm. Therefore the silver alloy material of the present invention is effectively used for the lines that are especially required to have low electric resistance, as in a liquid crystal display device used for a liquid crystal TV, for example.

The following will explain a method for forming the gate line 80 and the like in the present embodiment. Here, the pattern formation equipment typified by ink-jet pattern formation equipment is not used in the gate line formation step 102. Thus, a step corresponding to the gate line pre-processing step 101 is not performed.

First, silver alloy film containing indium in an amount of 0.2% by weight with respect to silver is formed to have a thickness of 0.2 μm on the glass substrate 12 by a sputtering method. Here, an alloy target prepared by dissolving indium into silver is used as the sputtering target. Next, titanium is continuously formed into films in a vacuum using a sputtering method. The thus obtained films are processed by photolithography, so that the gate line and the like as shown in FIGS. 41(a), 41(b), 42(a), and 42(b) are obtained. A dry etching method is used for the etching.

The terminal line 83 and the like require plasma resistance in view of the steps to be performed later. In the present embodiment, the plasma resistance is achieved by titanium of the upper layers.

As described above, the silver alloy material of the present invention may be used as a layer in a multilayer wiring structure. By setting an amount of indium with respect to silver to be not more than 0.5% by weight, it is possible to realize the lines having low electric resistance that cannot be realized by conventional aluminum lines.

Note that, in the foregoing formation method, the silver alloy film of the present invention is formed into a film directly on the glass substrate 12. But, if the adhesion to the substrate is not sufficiently obtained in this method, an intermediate layer made of metal, etc., may be provided between the glass substrate and the silver alloy film; or the surface of the glass substrate may be subjected to plasma treatment, chemical treatment, or other treatment in order to achieve the adhesion.

In the present invention, the material of the layers 80 b, 81 b, 82 b, and 83 b on the upper side is not limited to titanium, and may be chromium, molybdenum, tantalum, and tungsten; a material in which chromium, molybdenum, tantalum, or tungsten contains nitrogen and/or oxygen; or metal oxide such as ITO (indium tin oxide). The gate line 80 and the like may be formed in such a manner that fluid wiring material is applied and layered as in First Embodiment. As another example, the gate line 80 and the like may be formed by using an evaporation method using an evaporation source composed of silver and indium.

In the present embodiment, the lines are formed in the gate line formation step 102 using films composed of the silver alloy of the present invention and titanium. As another embodiment of the present invention, the lines composed of multilayer film may be similarly formed in the source and drain lines formation step 106. In this case, the alloy composed of silver and indium has heat resistance, and is not adversely affected by the baking in the steps to be performed later.

In this case, by setting an amount of indium with respect to silver to be not more than 0.5% by weight, it is equivalently possible to realize the lines having low electric resistance that cannot be realized by conventional aluminum lines.

Further, by causing silver to contain indium, it is possible to form a film having a higher reflectance after the baking compared with aluminum film. If the lines also serve as a reflecting plate or reflective electrodes, in particular, the lines should be formed using the silver alloy material containing indium in an amount of not more than 0.5% by weight with respect to silver.

As described above, a silver alloy material of the present invention for composing lines and/or electrodes formed on an insulation substrate is arranged so as to contain silver as a main component; and at least one element selected from the group consisting of tin, zinc, lead, bismuth, indium, and gallium.

With the material as arranged above, it is possible to form lines and/or electrodes that has low electric resistance, as well as high process resistance such as heat resistance, adhesion to a glass substrate, and plasma resistance.

The silver alloy material of the present invention may be arranged so that the element includes at least zinc.

In this case, if lines, electrodes, and the like, are formed using a silver alloy material containing silver as its main component and at least zinc, it is possible to improve heat resistance, adhesion, and plasma resistance under a condition in which chlorine gas or oxygen gas is introduced, without significantly losing the low electric resistance.

The silver alloy material of the present invention may be arranged so that the element includes at least indium.

In this case, if lines, electrodes, and the like, are formed using a silver alloy material containing silver as its main component and at least indium, it is possible to remarkably improve heat resistance, adhesion, and characteristically plasma resistance, without significantly losing the low electric resistance.

Further, by adding an appropriate amount of indium to silver, it is possible to obtain a silver alloy film retaining high visible light reflectance after baked at 200° C. or at 300° C. Further, because the silver alloy film as described above has high reflectance as a whole compared with aluminum conventionally used for a light reflecting film, brighter display can be achieved when the silver alloy film is used as light reflective electrodes, etc., in a reflection type liquid crystal display device, for example.

Further, the alloy material of silver and indium can cover wide ranges of heat resistance, adhesion, plasma resistance, and high visible light reflectance, if the content of indium with respect to silver is adjusted.

The silver alloy material of the present invention is preferably arranged so that a content of indium with respect to silver (indium/silver (weight %)) is in a range of not less than 0.5% by weight and not more than 28% by weight. If the content of indium is lowered, plasma resistance is lowered, but electric resistance can be reduced. However, if the content of indium is less than 0.5% by weight, there is a problem that plasma resistance is lowered too much. Further, if the content of indium is increased, the electric resistance value is raised, but the plasma resistance is increased. However, if the content of indium is more than 28% by weight with respect to silver, there is a problem that a solid solution cannot be formed with respect to silver. As described above, by appropriately adjusting the content of indium with respect to silver, it is possible to easily change the characteristics in accordance with portions which require different characteristics, such as the line section and terminal section on a circuit substrate.

The silver alloy material of the present invention may be arranged so that a composition range of silver and the element is set such that an electric resistivity of the silver alloy material is not more than 10 μΩcm.

In this case, in the conventional technique where aluminum or aluminum alloy is used for the lines, the electric resistivity is in a range of about from 4 μΩcm to 10 μΩcm. Therefore the silver alloy material of the present invention as described above can achieve desired electric properties, and can be introduced without the need for changes in the conventional wiring design.

The silver alloy material of the present invention may be arranged so as to include at least an element selected from the group consisting of aluminum, copper, nickel, gold, platinum, palladium, cobalt, rhodium, iridium, ruthenium, osmium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, and neodymium.

The elements as mentioned above are useful as an auxiliary material for further improving the heat resistance, adhesion, and plasma resistance of the silver alloy material. Therefore by containing at least one element of these elements, the silver alloy material can have further improved heat resistance, adhesion, and plasma resistance.

A circuit substrate of the present invention is arranged so as to include lines and/or electrodes composed of the silver alloy material as arranged above.

This circuit substrate can be arranged to have lines having low electric resistance. With this, it is possible to manufacture a large-sized circuit substrate as in the conventional technique in which the lines are formed using aluminum or aluminum alloy.

An electronic device of the present invention is arranged to use the foregoing circuit substrate.

The electronic device may be a display device and a liquid crystal display device, for example.

Further, dry etching method is used many times in the manufacturing of a TFT array substrate which is a circuit substrate constituting a liquid crystal display device. Accordingly, heat resistance, adhesion, and plasma resistance are required for the material of the lines and/or electrodes. Therefore it is quite useful for the liquid crystal display device to use the circuit substrate whose lines and electrodes are formed with the silver alloy material of the present invention.

A sputtering target of the present invention is arranged so as to contain silver as a main component; and at least one element selected from the group consisting of tin, zinc, lead, bismuth, indium, and gallium.

By using this silver alloy material as the sputtering target, it is possible to obtain lines having high process resistance. With this, it is possible to manufacture with high productivity, the circuit substrate, display device, and the like, of the present invention.

An evaporation source of the present invention is arranged so as to contain silver as a main component; and at least one element selected from the group consisting of tin, zinc, lead, bismuth, indium, and gallium.

By using this silver alloy material as the evaporation source, it is possible to obtain lines having high process resistance. With this, it is possible to manufacture with high productivity, the circuit substrate, display device, and the like, of the present invention.

A fluid metal-containing material of the present invention is arranged so as to contain silver as a main component; and at least one element selected from the group consisting of tin, zinc, lead, bismuth, indium, and gallium.

By using this silver alloy material as the fluid metal-containing material, it is possible to obtain lines having high process resistance. With this, it is possible to manufacture with high productivity, the circuit substrate, display device, and the like, of the present invention.

Further, the silver alloy of the present invention can be produced in a range where a primary solid solution mainly constituting of silver is formed. In this case, like silver, the silver alloy can be easily made into fluid form (ink form), and is suitably used as a material used in the process for forming lines using an ink-jet head.

A silver alloy material of the present invention for composing (A) lines and/or electrodes or (B) a light reflecting film formed on an insulation substrate is arranged so as to contain silver as a main component; and at least indium.

The silver alloy material of the present invention is preferably arranged so that a content of indium with respect to silver is not more than 0.5% by weight.

In this case, if the content of indium is less than 0.5% by weight, there is a problem that plasma resistance is lowered. However, if the content of indium is not more than 0.5% by weight, the silver alloy material can achieve a higher visible light reflectance than aluminum with respect to an almost overall range of visible light even after baked at 200° C.

Further, if the silver alloy material contains indium in a ratio of not more than 0.5% by weight with respect to silver, the silver alloy material can beneficially form the lines having low electric resistance that cannot be achieved by conventional aluminum lines. Therefore the silver alloy material of the present invention is effectively used for the lines that are especially required to have low electric resistance, as in a liquid crystal display device used for a liquid crystal TV, for example.

The silver alloy material of the present invention is preferably arranged so that a content of indium with respect to silver is not more than 0.2% by weight.

In this case, if the content of indium is not more than 0.2% by weight, the silver alloy material can achieve a higher visible light reflectance than aluminum with respect to an almost overall range of visible light even after baked at 300° C.

Therefore the silver alloy material can be used for light reflective electrodes (electrode structure that serves both as electrode and reflecting film), and can achieve brighter display than the conventional light reflective electrodes composed of aluminum.

A method for manufacturing a circuit substrate of the present invention is arranged so as to include the step of forming lines and/or electrodes on an insulation substrate using either the foregoing sputtering target or the foregoing evaporation source.

With this manufacturing method, it is possible to form on a circuit substrate, lines having high process resistance. With this, it is possible to manufacture circuit substrates with high productivity.

A method for manufacturing a circuit substrate of the present invention may be arranged so as to include the step of forming lines and/or electrodes on an insulation substrate using the foregoing fluid metal-containing material.

With this manufacturing method using the fluid metal-containing material, it is possible to form on a circuit substrate, lines having high process resistance. With this, it is possible to manufacture circuit substrates with high productivity.

Here, concrete examples of the circuit substrate are a TFT array substrate used in a liquid crystal display device, etc.; an electrode substrate, a printed wiring substrate, flexible wiring substrate, etc., used in a PDP (Plasma Display Panel).

Concrete examples of the display device and image input device manufactured using the foregoing circuit substrate is a display device such as a liquid crystal display device, a PDP (Plasma Display Panel), an organic EL (Electroluminescence) panel, and an inorganic EL panel; and a two-dimensional image input device typified by a fingerprint sensor and an X-ray imaging device.

The insulation substrate used in the implement of the present invention is an insulation substrate such as an alkali glass substrate, a nonalkali glass substrate, and a plastic substrate, but also includes a substrate used substantially for the same purpose as the insulation substrate, such as a metal substrate in which an insulation layer is coated on a surface on which lines are to be formed.

A circuit substrate of the present invention including lines formed on a substrate is arranged so that at least two portions in a same line have different characteristics from one another.

Here, the same line means a line having continuous shape, and a unit of a plurality of lines that form the circuit substrate.

It is possible to change characteristics of one portion from another in the same line by causing the portions to have different composition ratios from one another, or by causing the portions to have different component materials from one another.

For example, in a circuit substrate used as a circuit substrate in a liquid crystal display device, a line portion and a terminal portion in the same line require different characteristics from each other. The line portion requires low resistance, and does not require plasma resistance much, because a passivation film is formed thereon. On the other hand, the terminal portion does require low resistance, but more requires process resistance (plasma resistance, in particular) because, for connection with a driver IC, etc., the terminal portion is not protected by a passivation film.

Therefore the composition ratios of the wiring materials or component materials of the lines should be changed so that the line at the line portion has a characteristic having emphasis on low resistance, and the line at the terminal portion has a characteristic having emphasis on plasma resistance.

The circuit substrate of the present invention is preferably arranged so that the same line is composed of a single layer.

In this case, it is possible to reduce the thickness of the circuit substrate, and reduce a difference in level with respect to another line formed on the line. This prevents breaking of the other line due to the difference in level, thereby improving the yield of circuit substrates.

The circuit substrate of the present invention may be arranged so that the same line is composed of multiple layers.

If the adhesion of the wiring material to the substrate is not good, for example, the same line may be arranged to have a two-layer structure in which a layer having good adhesion to the substrate is formed between the substrate and the line made from wiring material, and the wiring material is applied thereon.

Further, the circuit substrate of the present invention is preferably arranged so that the lines are composed of fluid materials containing a conductive material.

Further, it is possible to easily form lines without layering another film, thereby easily reducing the number of manufacturing steps and manufacturing cost.

The circuit substrate of the present invention may be arranged so that the fluid materials containing the conductive material which are used for the portions having different characteristics contain a solvent and/or an organic matter in the same system.

In this case, even if the wiring materials have different characteristics from each other, the wiring materials having solvents in the same system can fit together well, and are not easily coagulated or separated. With this, it is possible to form the lines efficiently.

The circuit substrate of the present invention may be arranged so that the lines are composed of metal mainly consisting of silver, aluminum, or copper.

In this case, the lines are formed using the metal mainly consisting of either silver, aluminum, or copper that has comparatively low resistance. With this, it is possible to lower the resistance of the lines as a whole. Here, it is possible to adjust the surface flatness, plasma resistance, and adhesion by use of a component other than silver, aluminum, and copper that mainly compose the lines.

This component is preferably at least one metal selected from the group consisting of aluminum, indium, tin, bismuth, gallium, lead, copper, gold, silver, cobalt, nickel, palladium, platinum, rhodium, vanadium, titanium, zirconium, niobium, tantalum, tungsten, hafnium, osmium, and iridium.

Further, the inventors of the present invention found that in a case where alloy containing silver as its main component and indium is used as the wiring material for forming lines or electrodes on an insulation substrate, the adhesion of the lines and electrodes to the insulation substrate, as well as the heat resistance and plasma resistance of the lines and electrodes improved, compared with a case where a material consisting only silver is used for forming the lines or electrodes on the insulation substrate. Further, the inventors found that the similar effects can be achieved by using alloy in which tin, zinc, lead, bismuth, or gallium, instead of indium, is added to silver.

Therefore this silver alloy material is preferably used as the wiring material.

In particular, the circuit substrate of the present invention is preferably arranged so that the lines are composed of silver-indium alloy that contains silver as a main component and indium.

Further, the alloy material of silver and indium can cover wide ranges of surface flatness, heat resistance, adhesion, and plasma resistance, etc., if the content of indium with respect to silver is adjusted.

The silver alloy material of the present invention is preferably arranged so that a content of indium with respect to silver (indium/silver (weight %)) is in a range of not less than 0.5% by weight and not more than 28% by weight. If the content of indium is lowered, plasma resistance is lowered, but electric resistance can be reduced. However, if the content of indium is less than 0.5% by weight, there is a problem that plasma resistance is lowered too much. Further, if the content of indium is increased, the electric resistance value is raised, but the plasma resistance is increased. However, if the content of indium is more than 28% by weight, there is a problem that a solid solution cannot be formed with respect to silver. As described above, by appropriately adjusting the content of indium with respect to silver, it is possible to easily change the characteristics in accordance with portions which require different characteristics, such as the line portion and terminal portion in a line.

Further, if an ink-jet method is used to apply the wiring material, it is possible to separately use the wiring materials containing different amounts of indium easily, thereby easily forming the lines having different characteristics in accordance with each portion.

Further, if the circuit substrate as arranged above is applied to a TFT array substrate which requires (i) plasma resistance during the processing of the channel section and terminal section, (ii) low resistance for the line section, and (iii) the surface flatness for the gate electrode section, it is possible to improve the yield of TFT array substrates and reduce the cost for manufacturing the TFT array substrate.

Further, if the circuit substrate of the present invention is applied to a TFT array substrate as described above, advantages such as the improvement of the yield are obtained as described above. Therefore it is possible to suitably use the circuit substrate in other electronic devices and display devices such as liquid crystal display devices and plasma display devices.

The invention being thus described, it will be obvious that the same way may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims. 

1. A silver alloy material for composing lines and/or electrodes formed on an insulation substrate, comprising: silver as a main component; and at least one element selected from the group consisting of tin, zinc, lead, bismuth, indium, and gallium.
 2. The silver alloy material as set forth in claim 1, wherein: the element includes at least zinc.
 3. The silver alloy material as set forth in claim 1, wherein: the element includes at least indium.
 4. The silver alloy material as set forth in claim 3, wherein: a content of indium with respect to silver is in a range of not less than 0.5% by weight and not more than 28% by weight.
 5. The silver alloy material as set forth in claim 1, wherein: a composition range of silver and the element is set such that an electric resistivity of the silver alloy material is not more than 10 μΩcm.
 6. The silver alloy material as set forth in claim 1, further comprising: at least an element selected from the group consisting of aluminum, copper, nickel, gold, platinum, palladium, cobalt, rhodium, iridium, ruthenium, osmium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, and neodymium.
 7. A circuit substrate, comprising: lines and/or electrodes composed of a silver alloy material for composing lines and/or electrodes formed on an insulation substrate, the silver alloy material containing (i) silver as a main component and (ii) at least one element selected from the group consisting of tin, zinc, lead, bismuth, indium, and gallium.
 8. An electronic device, comprising: a circuit substrate which includes lines and/or electrodes composed of a silver alloy material for composing lines and/or electrodes formed on an insulation substrate, the silver alloy material containing (i) silver as a main component and (ii) at least one element selected from the group consisting of tin, zinc, lead, bismuth, indium, and gallium.
 9. A display device, comprising: a circuit substrate which includes lines and/or electrodes composed of a silver alloy material for composing lines and/or electrodes formed on an insulation substrate, the silver alloy material containing (i) silver as a main component and (ii) at least one element selected from the group consisting of tin, zinc, lead, bismuth, indium, and gallium, said circuit substrate being used as a circuit substrate for display.
 10. A liquid crystal display device, comprising: a circuit substrate which includes lines and/or electrodes composed of a silver alloy material for composing lines and/or electrodes formed on an insulation substrate, the silver alloy material containing (i) silver as a main component and (ii) at least one element selected from the group consisting of tin, zinc, lead, bismuth, indium, and gallium, said circuit substrate being used as a circuit substrate for liquid crystal display.
 11. A sputtering target for forming lines and/or electrodes, comprising: silver as a main component; and at least one element selected from the group consisting of tin, zinc, lead, bismuth, indium, and gallium.
 12. An evaporation source for forming lines and/or electrodes, comprising: silver as a main component; and at least one element selected from the group consisting of tin, zinc, lead, bismuth, indium, and gallium.
 13. A fluid metal-containing material for forming lines and/or electrodes, comprising: silver as a main component; and at least one element selected from the group consisting of tin, zinc, lead, bismuth, indium, and gallium.
 14. A method for manufacturing a circuit substrate, comprising the step of: forming lines and/or electrodes on an insulation substrate using either (A) a sputtering target for forming lines and/or electrodes, said sputtering target containing (i) silver as a main component and (ii) at least one element selected from the group consisting of tin, zinc, lead, bismuth, indium, and gallium; (B) an evaporation source for forming lines and/or electrodes, said evaporation source containing (i) silver as a main component and (ii) at least one element selected from the group consisting of tin, zinc, lead, bismuth, indium, and gallium; or (C) a fluid metal-containing material for forming lines and/or electrodes, said fluid metal-containing material containing (i) silver as a main component and (ii) at least one element selected from the group consisting of tin, zinc, lead, bismuth, indium, and gallium.
 15. A silver alloy material for composing (A) lines and/or electrodes or (B) a light reflecting film formed on an insulation substrate, comprising: silver as a main component; and at least indium.
 16. The silver alloy material as set forth in claim 15, wherein: a content of indium with respect to silver is not more than 0.5% by weight.
 17. The silver alloy material as set forth in claim 15, wherein: a content of indium with respect to silver is not more than 0.2% by weight.
 18. A circuit substrate, comprising: lines and/or electrodes composed of a silver alloy material for composing (A) lines and/or electrodes or (B) a light reflecting film formed on an insulation substrate, the silver alloy material containing (i) silver as a main component and (ii) at least indium in an amount of not more than 0.5% by weight with respect to silver.
 19. An electronic device, comprising: a circuit substrate which includes lines and/or electrodes composed of a silver alloy material for composing (A) lines and/or electrodes or (B) a light reflecting film formed on an insulation substrate, the silver alloy material containing (i) silver as a main component and (ii) at least indium in an amount of not more than 0.5% by weight with respect to silver.
 20. A display device, comprising: a circuit substrate which includes lines and/or electrodes composed of a silver alloy material for composing (A) lines and/or electrodes or (B) a light reflecting film formed on an insulation substrate, the silver alloy material containing (i) silver as a main component and (ii) at least indium in an amount of not more than 0.5% by weight with respect to silver, said circuit substrate being used as a circuit substrate for display.
 21. A liquid crystal display device, comprising: a circuit substrate which includes lines and/or electrodes composed of a silver alloy material for composing (A) lines and/or electrodes or (B) a light reflecting film formed on an insulation substrate, the silver alloy material containing (i) silver as a main component and (ii) at least indium in an amount of not more than 0.5% by weight with respect to silver, said circuit substrate being used as a circuit substrate for liquid crystal display.
 22. A display device, comprising: a light reflecting film composed of a silver alloy material for composing (A) lines and/or electrodes or (B) a light reflecting film formed on an insulation substrate, the silver alloy material containing (i) silver as a main component and (ii) at least indium in an amount of not more than 0.5% by weight with respect to silver, said light reflecting film being used for display.
 23. A display device, comprising: a light reflecting film composed of a silver alloy material for composing (A) lines and/or electrodes or (B) a light reflecting film formed on an insulation substrate, the silver alloy material containing (i) silver as a main component and (ii) at least indium in an amount of not more than 0.2% by weight with respect to silver, said light reflecting film being used for display.
 24. A circuit substrate including lines formed on a substrate, wherein: at least two portions in a same line have different characteristics from one another.
 25. A circuit substrate including lines formed on a substrate, wherein: at least two portions in a same line have different composition ratios from one another.
 26. A circuit substrate including lines formed on a substrate, wherein: at least two portions in a same line have different component materials from one another.
 27. The circuit substrate as set forth in claim 24, wherein: the same line is composed of a single layer.
 28. The circuit substrate as set forth in claim 24, wherein: the same line is composed of multiple layers.
 29. The circuit substrate as set forth in claim 24, wherein: the lines are composed of metal mainly consisting of silver, aluminum, or copper.
 30. The circuit substrate as set forth in claim 29, wherein: the lines are composed of alloy that contains the metal and at least one metal selected from the group consisting of aluminum, indium, tin, bismuth, gallium, lead, copper, gold, silver, cobalt, nickel, palladium, platinum, rhodium, vanadium, titanium, zirconium, niobium, tantalum, tungsten, hafnium, osmium, and iridium.
 31. The circuit substrate as set forth in claim 30, wherein: the lines are composed of silver-indium alloy that contains silver as a main component and indium.
 32. The circuit substrate as set forth in claim 31, wherein: the silver-indium alloy contains indium in an amount of not less than 0.5% by weight and not more than 28% by weight with respect to silver.
 33. The circuit substrate as set forth in claim 24, wherein: the lines are composed of fluid materials containing a conductive material.
 34. The circuit substrate as set forth in claim 33, wherein: the fluid materials containing the conductive material which are used for the portions having different characteristics contain a solvent and/or an organic matter in the same system.
 35. A method for manufacturing a circuit substrate that includes lines formed on the circuit substrate, comprising the step of: forming the lines using an ink-jet method, so that at least two portions in a same line have different characteristics from one another.
 36. An electronic device, comprising: a circuit substrate which includes lines formed on the circuit substrate, at least two portions in a same line having different characteristics from one another in said circuit substrate.
 37. A display device, comprising: a circuit substrate which includes lines formed on the circuit substrate, at least two portions in a same line having different characteristics from one another in said circuit substrate, said circuit substrate being used as a circuit substrate for display.
 38. A liquid crystal display device, comprising: a circuit substrate which includes lines formed on the circuit substrate, at least two portions in a same line having different characteristics from one another in said circuit substrate, said circuit substrate being used as a circuit substrate for liquid crystal display. 